CHIP Simulation Results

Thursday November 06 2025 16:04:48 UTC

GitHub Revision: `f0c640e`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.315m	0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.315m	0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	14.387s	0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	18.569s	0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	11.665s	0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.594m	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.594m	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.594m	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	31.680s	0	1	0.00
		chip_sw_example_manufacturer	2.247m	0	1	0.00
		chip_sw_example_concurrency	2.845m	1	1	100.00
		chip_sw_uart_smoketest_signed	9.464s	0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.550s	0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.320s	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.320s	0	1	0.00
V1	xbar_smoke	xbar_smoke	18.150s	1	1	100.00
V1		TOTAL		3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.258m	0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	45.188m	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.189m	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	10.722s	0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	15.280s	0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	11.447s	0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.385s	0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	2.970s	0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.970s	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.659m	0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.548m	0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.543m	0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.543m	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	1.960m	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	1.820m	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.974m	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	13.019s	0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	9.780s	0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	9.829m	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.071m	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	8.100m	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	8.100m	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	9.765s	0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	3.572m	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	3.572m	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.099m	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.637m	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.720m	1	1	100.00
		chip_sw_aes_idle	2.807m	1	1	100.00
		chip_sw_hmac_enc_idle	3.185m	1	1	100.00
		chip_sw_kmac_idle	2.750m	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	2.936m	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	2.967m	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	2.703m	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	2.909m	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	15.015s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.939s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.081s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	9.419s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.186s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	9.444s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.430s	0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.015s	0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.939s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.081s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	9.419s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.186s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	9.444s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.430s	0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	38.220s	0	1	0.00
		chip_sw_aes_enc_jitter_en	38.660s	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.260s	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.130s	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.030s	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.310s	0	1	0.00
		chip_sw_clkmgr_jitter	2.668m	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	5.257m	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	35.920s	0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	42.740s	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	42.880s	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	36.520s	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	36.710s	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	35.820s	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	9.694s	0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.607s	0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.614s	0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.475s	0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.720m	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.938m	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	3.572m	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	13.240s	0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.938m	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	9.642s	0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	9.499s	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.704s	0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.849s	0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	9.423s	0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.720m	0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.974m	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	5.744m	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.498m	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	5.200m	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.579m	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.720m	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.188s	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.624s	0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.720m	0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	9.067s	0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	5.200m	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.631s	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.074s	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.633s	0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.991s	0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	8.961s	0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9.488s	0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.624s	0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	10.470s	0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	11.274s	0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	10.470s	0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	10.470s	0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	10.470s	0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	4.470m	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	10.106s	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	21.025s	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.992s	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.692s	0	1	0.00
		chip_sw_lc_ctrl_transition	10.470s	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	4.488m	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	12.529m	1	1	100.00
		chip_sw_sram_ctrl_execution_main	10.077s	0	1	0.00
		chip_prim_tl_access	12.740m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.015s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.939s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.081s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	9.419s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.186s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	9.444s	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.430s	0	1	0.00
		chip_rv_dm_lc_disabled	9.829m	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.837m	1	1	100.00
		chip_sw_aes_enc_jitter_en	38.660s	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.435m	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.807m	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.708m	1	1	100.00
		chip_sw_hmac_enc_jitter_en	36.260s	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.185m	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.659m	1	1	100.00
		chip_sw_kmac_mode_kmac	3.496m	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	39.030s	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	4.488m	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	10.470s	0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	32.290s	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.838m	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.750m	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	5.472m	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	5.472m	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	10.106s	0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.091m	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.373s	0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	4.488m	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.130s	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	37.235m	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	38.220s	0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.720m	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.720m	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.720m	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	6.118m	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	12.529m	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	12.529m	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.299m	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.310s	0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.077s	0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.720m	0	1	0.00
		chip_sw_data_integrity_escalation	1.543m	0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	10.470s	0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	6.118m	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	4.488m	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	5.299m	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.748m	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	6.118m	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	4.488m	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	5.299m	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.748m	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	10.470s	0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.705s	0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	11.274s	0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	10.106s	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	21.025s	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.992s	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.692s	0	1	0.00
		chip_sw_lc_ctrl_transition	10.470s	0	1	0.00
		chip_prim_tl_access	12.740m	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	12.740m	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	10.075s	0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	9.802s	0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.607s	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	38.220s	0	1	0.00
		chip_sw_aes_enc_jitter_en	38.660s	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.260s	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.130s	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.030s	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.310s	0	1	0.00
		chip_sw_clkmgr_jitter	2.668m	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	2.869m	0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	2.869m	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	2.653m	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	2.669m	0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	5.297m	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	3.486m	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.754m	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.748m	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	5.744m	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	5.744m	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	2.362m	1	1	100.00
		chip_sw_aon_timer_smoketest	2.510m	1	1	100.00
		chip_sw_clkmgr_smoketest	2.075m	1	1	100.00
		chip_sw_csrng_smoketest	2.126m	1	1	100.00
		chip_sw_gpio_smoketest	2.439m	1	1	100.00
		chip_sw_hmac_smoketest	2.618m	1	1	100.00
		chip_sw_kmac_smoketest	2.508m	1	1	100.00
		chip_sw_otbn_smoketest	3.197m	1	1	100.00
		chip_sw_otp_ctrl_smoketest	2.175m	1	1	100.00
		chip_sw_rv_plic_smoketest	2.129m	1	1	100.00
		chip_sw_rv_timer_smoketest	2.875m	1	1	100.00
		chip_sw_rstmgr_smoketest	1.950m	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.204m	1	1	100.00
		chip_sw_uart_smoketest	2.223m	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	9.459s	0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	9.464s	0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.258m	0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.812s	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.417m	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.058m	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.281m	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.786m	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	9.811s	0	1	0.00
		chip_rv_dm_lc_disabled	9.829m	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	11.858s	0	1	0.00
		chip_sw_lc_walkthrough_prod	11.460s	0	1	0.00
		chip_sw_lc_walkthrough_prodend	10.011s	0	1	0.00
		chip_sw_lc_walkthrough_rma	9.815s	0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	9.811s	0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	8.460m	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	7.217m	1	1	100.00
		rom_volatile_raw_unlock	9.935s	0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	9.698s	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	35.906s	0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	42.312s	0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.690m	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	1.690m	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.320s	0	1	0.00
		chip_same_csr_outstanding	9.240s	0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.320s	0	1	0.00
		chip_same_csr_outstanding	9.240s	0	1	0.00
V2	xbar_base_random_sequence	xbar_random	2.717m	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.210s	1	1	100.00
		xbar_smoke_large_delays	4.579m	1	1	100.00
		xbar_smoke_slow_rsp	5.215m	1	1	100.00
		xbar_random_zero_delays	48.540s	1	1	100.00
		xbar_random_large_delays	10.858m	1	1	100.00
		xbar_random_slow_rsp	3.876m	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	20.130s	1	1	100.00
		xbar_error_and_unmapped_addr	1.579m	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.605m	1	1	100.00
		xbar_error_and_unmapped_addr	1.579m	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.844m	1	1	100.00
		xbar_access_same_device_slow_rsp	15.034m	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	3.020m	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	16.169m	1	1	100.00
		xbar_stress_all_with_error	12.697m	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	6.960s	1	1	100.00
		xbar_stress_all_with_reset_error	16.548m	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	10.918s	0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.595s	0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.397s	0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.888s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	9.467s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.570s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.262s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.287s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	9.698s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.413s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	9.814s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.460s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	9.948s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	50.701s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.097m	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.168m	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	54.347s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	44.839s	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.030m	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	42.994s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	40.630s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	39.236s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	56.376s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	48.484s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	37.878s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	44.127s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	32.872s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	30.436s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	11.732s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.187s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	9.994s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.570s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	10.570s	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	9.889s	0	1	0.00
		rom_e2e_asm_init_dev	12.532s	0	1	0.00
		rom_e2e_asm_init_prod	10.629s	0	1	0.00
		rom_e2e_asm_init_prod_end	10.367s	0	1	0.00
		rom_e2e_asm_init_rma	10.698s	0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	9.940s	0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	9.760s	0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	9.785s	0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	9.797s	0	1	0.00
V2		TOTAL		68	204	33.33
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.367m	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.140m	1	1	100.00
V2S		TOTAL		2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	9.783s	0	1	0.00
		rom_e2e_jtag_debug_dev	11.771s	0	1	0.00
		rom_e2e_jtag_debug_rma	12.607s	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	9.528s	0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.720m	0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	10.227s	0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	3.349m	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	10.301s	0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	9.972s	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	9.783s	0	1	0.00
		rom_e2e_jtag_debug_dev	11.771s	0	1	0.00
		rom_e2e_jtag_debug_rma	12.607s	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	9.987s	0	1	0.00
		rom_e2e_jtag_inject_dev	10.711s	0	1	0.00
		rom_e2e_jtag_inject_rma	9.904s	0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	9.923s	0	1	0.00
V3		TOTAL		0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	15.006m	0	1	0.00
		chip_sw_entropy_src_kat_test	2.485m	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.484m	1	1	100.00
		chip_plic_all_irqs_0	6.712m	1	1	100.00
		chip_plic_all_irqs_10	5.736m	1	1	100.00
		chip_plic_all_irqs_20	10.427s	0	1	0.00
		chip_sw_dma_inline_hashing	2.969m	1	1	100.00
		chip_sw_dma_abort	3.357m	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	9.370s	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	9.496s	0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	9.732s	0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	9.485s	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	9.722s	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	9.540s	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.115s	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	9.658s	0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	9.723s	0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	9.662s	0	1	0.00
		chip_sw_entropy_src_smoketest	2.784m	1	1	100.00
		chip_sw_mbx_smoketest	3.892m	1	1	100.00
		TOTAL		80	250	32.00

Failure Buckets

Job returned non-zero exit code has 131 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.66521485903107168007436724797133754567909850427541728640563584876631256482498
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 125.039s, Critical Path: 0.03s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.111987296111807175458962627719511557227868550761985381546570958897182403322427
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 83.786s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.94662890407592543613303280032373829821903312377394340077752198818128242759892
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 90.738s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.83998616395640493494247942773642717184276992878680904830354406308132114959824
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 84.209s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.44949728248451025084373405456646592647175506423766436468264174999768722521159
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 69.275s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 126 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 11 failures:
- Test chip_sw_otbn_ecdsa_op_irq_jitter_en has 1 failures.
  - 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.9182479425723947185315431856289923114696838458128098759320645365534085387122
    Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.43673548124880681760826695096022015005207731855947387733487972772413853084944
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.3738849329028325475451651969692310990801487717781044418549546805361095199866
    Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.30862122927520466644797006577895306214114944980841130965997584952041737985470
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.4440204730512080298654295186901007825782558733964835912271752098673337895151
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 6 failures:
- Test chip_sw_rstmgr_cpu_info has 1 failures.
  - 0.chip_sw_rstmgr_cpu_info.52355396835394913046467741940289537724826715271814257339252114611433691892364
    Line 422, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 375.216000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 375.216000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_soc_proxy_smoketest has 1 failures.
  - 0.chip_sw_soc_proxy_smoketest.34484421309213332917080529365361767629768765523640423767957975364585905546047
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
```
      Offending '((!rstreqs[1]) && (reset_cause != HwReq))'
  UVM_ERROR @ 143.376000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 143.376000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_aes_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_aes_trans.34247695263067927261773133410313734026563279851193255377099618818948674472502
    Line 411, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.696000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.696000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_hmac_trans.112322245003622871974372348648738208480411691422488397244654773405481953991605
    Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.680000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.680000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_kmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_kmac_trans.47061033134059337534384430346052038964286523747527158671215138009290306507964
    Line 414, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 1 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.105301538356562990422107651426471480624235914373076049152461760684233083797401
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.81543309254050845604055465016082272956413191016619199055891894782918489117217
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.7790333727360681607784261104903582416345473152527313442194069157003062105244
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 2 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.17269210867756746646747881989665693657738306391219189317680847214999736188336
    Line 450, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 905.627000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
  UVM_INFO @ 905.627000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.
  - 0.chip_sw_rstmgr_rst_cnsty_escalation.44094803347714468751971150860134586699569852952126008229829866944400736858460
    Line 433, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
```
  UVM_ERROR @ 905.862000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
  UVM_INFO @ 905.862000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.46707803031058031374191938305511285829375541813857924440679860438848891059810
Line 416, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 268.231000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1396317177542960367823158058468068485279188573180357787994592134355901549115683053945273744772370294494400647574077202112618847460934066230276933554625628 [0x1aa90e62aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd39cffbe937f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 268.231000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.89859626160769444842733721839466170028979250092212192282511833084549324109204
Line 412, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 268.212000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (5049085807673756555928258451058800433919058474129503304496458424257095262477096766458976807287037151362037784330232245751117738042936030972387843023133788 [0x60676ad6aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3e631da277f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 268.212000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42095) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.28772913911395465162147001228627625294469966966736411839747735666686328675137
Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 117.026000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42095) { a_addr: 'h30480000  a_data: 'h337ec114  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc  a_opcode: 'h1  a_user: 'h24897  d_param: 'h0  d_source: 'hc  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 117.026000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.81191101156815425539806616883347805231697165929250735673657892148460666866751
Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 117.017000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42095) { a_addr: 'h30480000  a_data: 'h2db39230  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h1  a_user: 'h248e2  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 117.017000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.15605396100938104927592991830123225054493579395066368072891869617660756513375
    Line 567, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.71200398773560736448622727162150304116431165977961707454212265581253426959434
    Line 421, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 287.320000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 287.320000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.88300924356408279731001079342614577809970341538596683656610940427018994512001
    Line 407, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 158.236000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 158.236000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.10575344387670188623673075171318730556948131368558024860706159483356721953209
    Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 290.158000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
  UVM_INFO @ 290.158000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.555616096871056248591103138002431977042267975301720783574466560372641259935
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 138.787000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 138.787000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns * has 1 failures:
- Test chip_sw_soc_proxy_gpios has 1 failures.
  - 0.chip_sw_soc_proxy_gpios.59285628883249955722539863039132212396710462753628960196007431150727732310574
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log
```
  UVM_ERROR @ 136.441000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
  UVM_INFO @ 136.441000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 1 failures:
- Test chip_sw_aon_timer_irq has 1 failures.
  - 0.chip_sw_aon_timer_irq.35243599443949866357530972091434577315231325302312680399973885601868958235360
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
```
  UVM_ERROR @ 574.573000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4345 usec which is not in the range 397 usec and 452 usec
  UVM_INFO @ 574.573000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.52826154760884487285369897230517193453360163980406768786026914158797492955392
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 164.341000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 164.341000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.4363440658950421801177938201786562545520744599732756024545533997967143046552
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 251.586000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 251.586000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.3134672437797449227984780688165374606231608072362506618933640614118936814449
    Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.82677305125080448853315459085410583987974361763158886331847163611054811758849
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 118.329000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 118.329000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.24042500393270331819605907692861935183781429636522611571329040695147589664367
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_ERROR @ * us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.15489899791194753134153136847761737800615584844338151371617361179418332975278
    Line 414, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_ERROR @ 195.744000 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 195.744000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```