DMA Simulation Results

Monday November 10 2025 16:01:52 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	1.031ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	363.355us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	6.000s	1.251ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	16.122us	1	1	100.00
V1	csr_rw	dma_csr_rw	3.000s	15.015us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	10.000s	1.156ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	5.000s	540.733us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	3.000s	147.139us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	3.000s	15.015us	1	1	100.00
		dma_csr_aliasing	5.000s	540.733us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	57.000s	4.679ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	7.600m	152.204ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	9.317m	116.318ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	9.317m	116.318ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	7.600m	152.204ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	6.833m	138.161ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	9.317m	116.318ms	1	1	100.00
V2	dma_abort	dma_abort	12.000s	984.292us	1	1	100.00
V2	dma_stress_all	dma_stress_all	5.033m	27.689ms	1	1	100.00
V2	alert_test	dma_alert_test	3.000s	18.345us	1	1	100.00
V2	intr_test	dma_intr_test	2.000s	15.305us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	235.040us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	235.040us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	16.122us	1	1	100.00
		dma_csr_rw	3.000s	15.015us	1	1	100.00
		dma_csr_aliasing	5.000s	540.733us	1	1	100.00
		dma_same_csr_outstanding	3.000s	23.569us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	16.122us	1	1	100.00
		dma_csr_rw	3.000s	15.015us	1	1	100.00
		dma_csr_aliasing	5.000s	540.733us	1	1	100.00
		dma_same_csr_outstanding	3.000s	23.569us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	16.000s	288.350us	1	1	100.00
		dma_generic_stress	6.833m	138.161ms	1	1	100.00
		dma_handshake_stress	9.317m	116.318ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	9.000s	4.144ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	120.360us	1	1	100.00
		dma_sec_cm	3.000s	61.932us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.033m	13.815ms	1	1	100.00
		dma_longer_transfer	4.000s	83.683us	1	1	100.00
		dma_stress_all_with_rand_reset	17.000s	3.249ms	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.78806421220704764412825108952531956674260655552603198773543949029265834366517
      Line 117, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3249091887ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3249091887ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---