I2C Simulation Results

Monday November 10 2025 16:01:52 UTC

GitHub Revision: `3c586cb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	23.280s	1	1	100.00
V1	target_smoke	i2c_target_smoke	7.690s	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.740s	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.730s	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	1.990s	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.010s	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.780s	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.730s	1	1	100.00
		i2c_csr_aliasing	1.010s	1	1	100.00
V1		TOTAL		7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.120s	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	2.174m	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.535m	1	1	100.00
V2	host_override	i2c_host_override	0.630s	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	58.760s	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	25.550s	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.950s	1	1	100.00
		i2c_host_fifo_fmt_empty	10.910s	1	1	100.00
		i2c_host_fifo_reset_rx	2.070s	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.905m	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	23.190s	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.690s	0	1	0.00
V2	target_glitch	i2c_target_glitch	1.800s	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	38.810s	0	1	0.00
V2	target_maxperf	i2c_target_perf	3.540s	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	12.990s	1	1	100.00
		i2c_target_intr_smoke	5.020s	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.790s	1	1	100.00
		i2c_target_fifo_reset_tx	1.070s	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	20.220s	1	1	100.00
		i2c_target_stress_rd	12.990s	1	1	100.00
		i2c_target_intr_stress_wr	2.443m	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.170s	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	15.080s	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.910s	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.230s	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.810s	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.890s	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.535m	1	1	100.00
		i2c_host_perf_precise	1.370s	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	23.190s	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	0.960s	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.850s	1	1	100.00
		i2c_target_nack_acqfull_addr	1.780s	1	1	100.00
		i2c_target_nack_txstretch	1.030s	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.580s	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.500s	1	1	100.00
V2	alert_test	i2c_alert_test	0.610s	1	1	100.00
V2	intr_test	i2c_intr_test	0.660s	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.080s	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.080s	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.740s	1	1	100.00
		i2c_csr_rw	0.730s	1	1	100.00
		i2c_csr_aliasing	1.010s	1	1	100.00
		i2c_same_csr_outstanding	1.020s	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.740s	1	1	100.00
		i2c_csr_rw	0.730s	1	1	100.00
		i2c_csr_aliasing	1.010s	1	1	100.00
		i2c_same_csr_outstanding	1.020s	1	1	100.00
V2		TOTAL		33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.680s	1	1	100.00
		i2c_sec_cm	0.830s	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.680s	1	1	100.00
V2S		TOTAL		2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	35.090s	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.730s	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	0.730s	0	1	0.00
V3		TOTAL		0	3	0.00
		TOTAL		42	50	84.00

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 4 failures:

Test i2c_host_error_intr has 1 failures.

0.i2c_host_error_intr.80658176372632447500315468484344648438431684998978099324059592152537505139611
Line 107, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  43341987 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  43341987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.105443503364118686237818626778851328750087164826505155958323317599941751354353
Line 136, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 26066911554 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 26066911554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_target_stress_all_with_rand_reset has 1 failures.
- 0.i2c_target_stress_all_with_rand_reset.113032338386142719705773678218841189316582442384006065337715568434597219573791
  Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @   4783984 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @   4783984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.88695584251097904677025832313192597185522055875076161726116924284399975208113
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  15496431 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  15496431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test i2c_target_glitch has 1 failures.
  - 0.i2c_target_glitch.79933243591850698514139552220916147621767239844387940676378072432769597555530
    Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
```
  UVM_ERROR @ 4568044234 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 4568044234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.35961952608834336919212247452177992817794177532983345492406579283056132749960
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  49710532 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  49710532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
- Test i2c_target_stress_all has 1 failures.
  - 0.i2c_target_stress_all.88950485801589332023599454917079171340502649241946729726774828600704158936300
    Line 98, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 17700575203 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 17700575203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.115238822421251052932623876032593696078701851915254178292014288045642993668148
    Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4669837793 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4669837793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```