KMAC/UNMASKED Simulation Results

Monday November 10 2025 16:01:52 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 31.860s 1 1 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.000s 1 1 100.00
V1 csr_rw kmac_csr_rw 1.130s 1 1 100.00
V1 csr_bit_bash kmac_csr_bit_bash 14.020s 1 1 100.00
V1 csr_aliasing kmac_csr_aliasing 2.980s 1 1 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 1.910s 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.130s 1 1 100.00
kmac_csr_aliasing 2.980s 1 1 100.00
V1 mem_walk kmac_mem_walk 0.840s 1 1 100.00
V1 mem_partial_access kmac_mem_partial_access 1.340s 1 1 100.00
V1 TOTAL 8 8 100.00
V2 long_msg_and_output kmac_long_msg_and_output 2.552m 1 1 100.00
V2 burst_write kmac_burst_write 9.715m 1 1 100.00
V2 test_vectors kmac_test_vectors_sha3_224 26.760s 1 1 100.00
kmac_test_vectors_sha3_256 28.690s 1 1 100.00
kmac_test_vectors_sha3_384 22.260s 1 1 100.00
kmac_test_vectors_sha3_512 14.190s 1 1 100.00
kmac_test_vectors_shake_128 2.656m 1 1 100.00
kmac_test_vectors_shake_256 24.460m 1 1 100.00
kmac_test_vectors_kmac 1.820s 1 1 100.00
kmac_test_vectors_kmac_xof 1.950s 1 1 100.00
V2 sideload kmac_sideload 1.581m 1 1 100.00
V2 app kmac_app 1.966m 1 1 100.00
V2 app_with_partial_data kmac_app_with_partial_data 34.040s 1 1 100.00
V2 entropy_refresh kmac_entropy_refresh 2.531m 1 1 100.00
V2 error kmac_error 2.131m 1 1 100.00
V2 key_error kmac_key_error 5.530s 1 1 100.00
V2 sideload_invalid kmac_sideload_invalid 2.030s 1 1 100.00
V2 edn_timeout_error kmac_edn_timeout_error 2.730s 1 1 100.00
V2 entropy_mode_error kmac_entropy_mode_error 20.660s 1 1 100.00
V2 entropy_ready_error kmac_entropy_ready_error 25.110s 1 1 100.00
V2 lc_escalation kmac_lc_escalation 1.270s 1 1 100.00
V2 stress_all kmac_stress_all 8.840m 1 1 100.00
V2 intr_test kmac_intr_test 0.880s 1 1 100.00
V2 alert_test kmac_alert_test 1.030s 1 1 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 1.710s 1 1 100.00
V2 tl_d_illegal_access kmac_tl_errors 1.710s 1 1 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.000s 1 1 100.00
kmac_csr_rw 1.130s 1 1 100.00
kmac_csr_aliasing 2.980s 1 1 100.00
kmac_same_csr_outstanding 1.500s 1 1 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.000s 1 1 100.00
kmac_csr_rw 1.130s 1 1 100.00
kmac_csr_aliasing 2.980s 1 1 100.00
kmac_same_csr_outstanding 1.500s 1 1 100.00
V2 TOTAL 26 26 100.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.820s 1 1 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.820s 1 1 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.820s 1 1 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.820s 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 2.410s 1 1 100.00
V2S tl_intg_err kmac_sec_cm 46.200s 1 1 100.00
kmac_tl_intg_err 2.440s 1 1 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 2.440s 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 1.270s 1 1 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 31.860s 1 1 100.00
V2S sec_cm_key_sideload kmac_sideload 1.581m 1 1 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.820s 1 1 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 46.200s 1 1 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 46.200s 1 1 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 46.200s 1 1 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 31.860s 1 1 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 1.270s 1 1 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 46.200s 1 1 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 2.286m 1 1 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 31.860s 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 1.444m 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 40 40 100.00