MBX Simulation Results

Monday November 10 2025 16:01:52 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	43.000s	7.742ms	1	1	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	3.000s	43.388us	1	1	100.00
V1	csr_rw	mbx_csr_rw	3.000s	17.472us	1	1	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	3.000s	151.700us	1	1	100.00
V1	csr_aliasing	mbx_csr_aliasing	3.000s	37.432us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	2.000s	35.140us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	3.000s	17.472us	1	1	100.00
		mbx_csr_aliasing	3.000s	37.432us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	mbx_stress	mbx_stress	1.983m	13.059ms	1	1	100.00
V2	mbx_max_activity	mbx_stress_zero_delays	8.000s	165.031us	0	1	0.00
V2	mbx_imbx_oob	mbx_imbx_oob	7.000s	43.907us	0	1	0.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	23.000s	2.140ms	1	1	100.00
V2	alert_test	mbx_alert_test	5.000s	23.909us	1	1	100.00
V2	intr_test	mbx_intr_test	2.000s	25.921us	1	1	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	4.000s	48.994us	1	1	100.00
V2	tl_d_illegal_access	mbx_tl_errors	4.000s	48.994us	1	1	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	3.000s	43.388us	1	1	100.00
		mbx_csr_rw	3.000s	17.472us	1	1	100.00
		mbx_csr_aliasing	3.000s	37.432us	1	1	100.00
		mbx_same_csr_outstanding	3.000s	32.030us	1	1	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	3.000s	43.388us	1	1	100.00
		mbx_csr_rw	3.000s	17.472us	1	1	100.00
		mbx_csr_aliasing	3.000s	37.432us	1	1	100.00
		mbx_same_csr_outstanding	3.000s	32.030us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	mbx_tl_intg_err	3.000s	172.719us	1	1	100.00
		mbx_sec_cm	5.000s	39.332us	1	1	100.00
V2S		TOTAL			2	2	100.00
		TOTAL			14	16	87.50

Failure Buckets

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 2 failures:

  • Test mbx_stress_zero_delays has 1 failures.

    • 0.mbx_stress_zero_delays.28872351359721479680937426451321831228568831302714385208414225699141619806642
      Line 225, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log

        UVM_ERROR @ 165031078 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 165031078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test mbx_imbx_oob has 1 failures.

    • 0.mbx_imbx_oob.22737314321481848244016425013664369744334351273646167188631056513873189384288
      Line 86, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log

        UVM_ERROR @  43906536 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @  43906536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---