OTBN Simulation Results

Monday November 10 2025 16:01:52 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 8.000s 275.920us 0 1 0.00
V1 single_binary otbn_single 9.000s 33.625us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 3.000s 20.069us 1 1 100.00
V1 csr_rw otbn_csr_rw 7.000s 34.429us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 4.000s 58.231us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 15.393us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 4.000s 88.982us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 7.000s 34.429us 1 1 100.00
otbn_csr_aliasing 4.000s 15.393us 1 1 100.00
V1 mem_walk otbn_mem_walk 15.000s 629.511us 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 9.000s 253.175us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 23.000s 317.922us 0 1 0.00
V2 multi_error otbn_multi_err 50.000s 305.056us 0 1 0.00
V2 back_to_back otbn_multi 55.000s 502.131us 0 1 0.00
V2 stress_all otbn_stress_all 57.000s 754.567us 0 1 0.00
V2 lc_escalation otbn_escalate 5.000s 16.608us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 5.000s 19.750us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 7.000s 43.750us 0 1 0.00
V2 alert_test otbn_alert_test 4.000s 15.481us 1 1 100.00
V2 intr_test otbn_intr_test 3.000s 14.323us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 4.000s 32.446us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 4.000s 32.446us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 3.000s 20.069us 1 1 100.00
otbn_csr_rw 7.000s 34.429us 1 1 100.00
otbn_csr_aliasing 4.000s 15.393us 1 1 100.00
otbn_same_csr_outstanding 4.000s 68.456us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 3.000s 20.069us 1 1 100.00
otbn_csr_rw 7.000s 34.429us 1 1 100.00
otbn_csr_aliasing 4.000s 15.393us 1 1 100.00
otbn_same_csr_outstanding 4.000s 68.456us 1 1 100.00
V2 TOTAL 6 11 54.55
V2S mem_integrity otbn_imem_err 6.000s 16.455us 0 1 0.00
otbn_dmem_err 7.000s 53.407us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 5.000s 52.633us 0 1 0.00
otbn_controller_ispr_rdata_err 7.000s 28.964us 0 1 0.00
otbn_mac_bignum_acc_err 31.000s 151.125us 0 1 0.00
otbn_urnd_err 8.000s 46.949us 0 1 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 4.000s 13.783us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 5.000s 38.827us 0 1 0.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 5.000s 227.933us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 10.000s 197.248us 0 1 0.00
otbn_tl_intg_err 15.000s 220.352us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 11.000s 136.677us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 10.000s 197.248us 0 1 0.00
V2S prim_count_check otbn_sec_cm 10.000s 197.248us 0 1 0.00
V2S sec_cm_mem_scramble otbn_smoke 8.000s 275.920us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 7.000s 53.407us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 6.000s 16.455us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 15.000s 220.352us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 5.000s 16.608us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 6.000s 16.455us 0 1 0.00
otbn_dmem_err 7.000s 53.407us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 19.750us 1 1 100.00
otbn_illegal_mem_acc 4.000s 13.783us 1 1 100.00
otbn_sec_cm 10.000s 197.248us 0 1 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 10.000s 197.248us 0 1 0.00
V2S sec_cm_scramble_key_sideload otbn_single 9.000s 33.625us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 6.000s 16.455us 0 1 0.00
otbn_dmem_err 7.000s 53.407us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 19.750us 1 1 100.00
otbn_illegal_mem_acc 4.000s 13.783us 1 1 100.00
otbn_sec_cm 10.000s 197.248us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 10.000s 197.248us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 5.000s 16.608us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 6.000s 16.455us 0 1 0.00
otbn_dmem_err 7.000s 53.407us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 19.750us 1 1 100.00
otbn_illegal_mem_acc 4.000s 13.783us 1 1 100.00
otbn_sec_cm 10.000s 197.248us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 10.000s 197.248us 0 1 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 9.000s 33.625us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 6.000s 71.403us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 5.000s 20.917us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 34.000s 1.059ms 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 34.000s 1.059ms 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 7.000s 68.784us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 10.000s 197.248us 0 1 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 10.000s 197.248us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 7.000s 61.288us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 10.000s 197.248us 0 1 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 10.000s 197.248us 0 1 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 5.000s 19.232us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 5.000s 19.232us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 6.000s 21.797us 0 1 0.00
V2S sec_cm_data_mem_sec_wipe otbn_single 9.000s 33.625us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 9.000s 33.625us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 9.000s 33.625us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 55.000s 502.131us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 9.000s 33.625us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 9.000s 33.625us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 5.000s 32.371us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 9.000s 33.625us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 10.000s 197.248us 0 1 0.00
V2S TOTAL 5 20 25.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 56.000s 381.624us 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 18 41 43.90

Failure Buckets