3c586cb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 3.660s | 1 | 1 | 100.00 | |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 2.360s | 1 | 1 | 100.00 | |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.870s | 1 | 1 | 100.00 | |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 3.680s | 1 | 1 | 100.00 | |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.440s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 2.380s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 2.970s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 4.750s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 54.250s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 1.570s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 1.080s | 1 | 1 | 100.00 | |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 0.770s | 1 | 1 | 100.00 | |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 2.320s | 0 | 1 | 0.00 | |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.010s | 1 | 1 | 100.00 | |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 2.460s | 1 | 1 | 100.00 | |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.950s | 1 | 1 | 100.00 | |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 1.690s | 1 | 1 | 100.00 | |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 1.570s | 1 | 1 | 100.00 | |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.760s | 1 | 1 | 100.00 | |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 1.230s | 1 | 1 | 100.00 | |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 0.770s | 1 | 1 | 100.00 | |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.900s | 1 | 1 | 100.00 | |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.220s | 1 | 1 | 100.00 | |
| V1 | csr_rw | rv_dm_csr_rw | 1.370s | 1 | 1 | 100.00 | |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 30.280s | 1 | 1 | 100.00 | |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 42.180s | 1 | 1 | 100.00 | |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 1.090s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 42.180s | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 1.370s | 1 | 1 | 100.00 | |||
| V1 | mem_walk | rv_dm_mem_walk | 0.760s | 1 | 1 | 100.00 | |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.920s | 1 | 1 | 100.00 | |
| V1 | TOTAL | 25 | 27 | 92.59 | |||
| V2 | idcode | rv_dm_smoke | 3.660s | 1 | 1 | 100.00 | |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 0.970s | 1 | 1 | 100.00 | |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 1.090s | 1 | 1 | 100.00 | |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 1.070s | 1 | 1 | 100.00 | |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 1.370s | 1 | 1 | 100.00 | |
| V2 | sba | rv_dm_sba_tl_access | 2.753m | 0 | 1 | 0.00 | |
| rv_dm_delayed_resp_sba_tl_access | 4.464m | 0 | 1 | 0.00 | |||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 5.159m | 0 | 1 | 0.00 | |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 9.092m | 0 | 1 | 0.00 | |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.810s | 0 | 1 | 0.00 | |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 3.610s | 1 | 1 | 100.00 | |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 1.160s | 1 | 1 | 100.00 | |
| V2 | hart_unavail | rv_dm_hart_unavail | 1.040s | 0 | 1 | 0.00 | |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 9.670s | 0 | 1 | 0.00 | |
| rv_dm_tap_fsm_rand_reset | 0.930s | 0 | 1 | 0.00 | |||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 0.780s | 1 | 1 | 100.00 | |
| V2 | stress_all | rv_dm_stress_all | 1.170s | 0 | 1 | 0.00 | |
| V2 | alert_test | rv_dm_alert_test | 1.050s | 1 | 1 | 100.00 | |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 1.120s | 0 | 1 | 0.00 | |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 1.120s | 0 | 1 | 0.00 | |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 42.180s | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 2.220s | 1 | 1 | 100.00 | |||
| rv_dm_csr_rw | 1.370s | 1 | 1 | 100.00 | |||
| rv_dm_same_csr_outstanding | 3.150s | 1 | 1 | 100.00 | |||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 42.180s | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 2.220s | 1 | 1 | 100.00 | |||
| rv_dm_csr_rw | 1.370s | 1 | 1 | 100.00 | |||
| rv_dm_same_csr_outstanding | 3.150s | 1 | 1 | 100.00 | |||
| V2 | TOTAL | 9 | 19 | 47.37 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 3.900s | 1 | 1 | 100.00 | |
| rv_dm_tl_intg_err | 7.300s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 7.300s | 0 | 1 | 0.00 | |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 3.610s | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 0.940s | 1 | 1 | 100.00 | |||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 3.610s | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 0.940s | 1 | 1 | 100.00 | |||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 3.660s | 1 | 1 | 100.00 | |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 1.020s | 1 | 1 | 100.00 | |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.810s | 1 | 1 | 100.00 | |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.810s | 1 | 1 | 100.00 | |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 1.020s | 1 | 1 | 100.00 | |
| V2S | TOTAL | 4 | 5 | 80.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 0.990s | 0 | 1 | 0.00 | |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 4.494m | 0 | 1 | 0.00 | ||
| TOTAL | 38 | 53 | 71.70 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
Test rv_dm_sba_tl_access has 1 failures.
0.rv_dm_sba_tl_access.74281668438886337998851117930051839787237190909890784735820262940556735874108
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
0.rv_dm_delayed_resp_sba_tl_access.86790640785817871903790989446127037244148392815052758977883230865720091405936
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_bad_sba_tl_access has 1 failures.
0.rv_dm_bad_sba_tl_access.82932057932783411634021277478989423253115637321653673111088043667365314014236
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
0.rv_dm_autoincr_sba_tl_access.93040252981684102628660665024551517932568177287357600804753627860551313693930
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_scanmode has 1 failures.
0.rv_dm_scanmode.101452045306841662100560776927724299482050338437249420221440653193463326472584
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_scanmode/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 2 failures:
Test rv_dm_jtag_dmi_debug_disabled has 1 failures.
0.rv_dm_jtag_dmi_debug_disabled.73197390270434387260518573883891329870277635030095538066561879286069102795246
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 79112876 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2480386764 [0x93d7b2cc] vs 0 [0x0])
UVM_INFO @ 79112876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
0.rv_dm_stress_all.73762212259006406675682658838390701465482616230532444449999040477918872396547
Line 75, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 414080944 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2190450845 [0x828fa09d] vs 0 [0x0])
UVM_INFO @ 414080944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access has 1 failures:
0.rv_dm_tap_fsm.4751727413534052348270472963087036142060366044704240343838515117990109385379
Line 113, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
Error-[NOA] Null object access
src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, 652
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5762) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tap_fsm_rand_reset.12852336582140685308854757693333359283557884935066307977481968137718352875063
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 33081815 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5762) { a_addr: 'h85ead7b8 a_data: 'hd8e55f23 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf7 a_opcode: 'h4 a_user: 'h18f6b d_param: 'h0 d_source: 'hf7 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 33081815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs * [])` has 1 failures:
0.rv_dm_mem_tl_access_resuming.10551736555073931773792848522922118823866385083184418445804359990029984820253
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log
UVM_ERROR @ 390182534 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 390182534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 1 failures:
0.rv_dm_hart_unavail.66534547479901622409072084740687168223850565869940937251752466028835258638821
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 100733978 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 100733978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5748) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_stress_all_with_rand_reset.92282560554195748778893006345872780747129952657893712008405780932641726711869
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 79602805 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5748) { a_addr: 'h2fd6e77c a_data: 'ha0cfae7f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hea a_opcode: 'h4 a_user: 'h1bff0 d_param: 'h0 d_source: 'hea d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 79602805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5874) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tl_errors.8494874885481535525924277542959470655481477027785229461472039469515622341332
Line 75, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log
UVM_ERROR @ 58955055 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5874) { a_addr: 'h8e5fb4a4 a_data: 'h4990af27 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hfc a_opcode: 'h4 a_user: 'h1aeb0 d_param: 'h0 d_source: 'hfc d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 58955055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [rv_dm_common_vseq] expect alert:fatal_fault to fire has 1 failures:
0.rv_dm_tl_intg_err.2818960955093030567140036170826303261071160164318590359526878986134440658193
Line 157, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest/run.log
UVM_ERROR @ 3548281298 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 3548281298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@7026) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_csr_mem_rw_with_rand_reset.14306797189627508925552877163447968447104233072492385839301732021003149411584
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 148077212 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@7026) { a_addr: 'h72992588 a_data: 'h3437e947 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h11 a_opcode: 'h4 a_user: 'h1b200 d_param: 'h0 d_source: 'h11 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 148077212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---