SPI_HOST Simulation Results

Monday November 10 2025 16:01:52 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	3.000s	575.563us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	144.517us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	33.204us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	302.294us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	45.282us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	29.738us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	33.204us	1	1	100.00
		spi_host_csr_aliasing	2.000s	45.282us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	67.395us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	24.582us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	55.469us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.000s	332.064us	1	1	100.00
		spi_host_error_cmd	2.000s	18.740us	1	1	100.00
		spi_host_event	3.533m	30.008ms	1	1	100.00
V2	clock_rate	spi_host_speed	3.000s	166.468us	1	1	100.00
V2	speed	spi_host_speed	3.000s	166.468us	1	1	100.00
V2	chip_select_timing	spi_host_speed	3.000s	166.468us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	10.000s	656.119us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	281.165us	1	1	100.00
V2	cpol_cpha	spi_host_speed	3.000s	166.468us	1	1	100.00
V2	full_cycle	spi_host_speed	3.000s	166.468us	1	1	100.00
V2	duplex	spi_host_smoke	3.000s	575.563us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	3.000s	575.563us	1	1	100.00
V2	stress_all	spi_host_stress_all	4.000s	421.454us	1	1	100.00
V2	spien	spi_host_spien	3.000s	437.770us	1	1	100.00
V2	stall	spi_host_status_stall	1.233m	9.319ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	355.434us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.000s	332.064us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	33.487us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	16.060us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	27.631us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	27.631us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	144.517us	1	1	100.00
		spi_host_csr_rw	2.000s	33.204us	1	1	100.00
		spi_host_csr_aliasing	2.000s	45.282us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	97.863us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	144.517us	1	1	100.00
		spi_host_csr_rw	2.000s	33.204us	1	1	100.00
		spi_host_csr_aliasing	2.000s	45.282us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	97.863us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	165.955us	1	1	100.00
		spi_host_sec_cm	3.000s	72.883us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	165.955us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	31.000s	2.650ms	1	1	100.00
		TOTAL			26	26	100.00