SRAM_CTRL/MAIN Simulation Results

Monday November 10 2025 16:01:52 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 4.130s 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.810s 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 0.910s 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.190s 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.700s 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.060s 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.910s 1 1 100.00
sram_ctrl_csr_aliasing 0.700s 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 1.794m 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 56.410s 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 8.055m 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 3.054m 1 1 100.00
V2 bijection sram_ctrl_bijection 9.944m 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 7.648m 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 19.300s 1 1 100.00
V2 executable sram_ctrl_executable 6.809m 1 1 100.00
V2 partial_access sram_ctrl_partial_access 26.320s 1 1 100.00
sram_ctrl_partial_access_b2b 6.056m 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 45.130s 1 1 100.00
sram_ctrl_throughput_w_partial_write 35.920s 1 1 100.00
sram_ctrl_throughput_w_readback 1.195m 1 1 100.00
V2 regwen sram_ctrl_regwen 8.844m 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 2.560s 1 1 100.00
V2 stress_all sram_ctrl_stress_all 36.804m 1 1 100.00
V2 alert_test sram_ctrl_alert_test 0.870s 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 3.230s 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 3.230s 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.810s 1 1 100.00
sram_ctrl_csr_rw 0.910s 1 1 100.00
sram_ctrl_csr_aliasing 0.700s 1 1 100.00
sram_ctrl_same_csr_outstanding 0.850s 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.810s 1 1 100.00
sram_ctrl_csr_rw 0.910s 1 1 100.00
sram_ctrl_csr_aliasing 0.700s 1 1 100.00
sram_ctrl_same_csr_outstanding 0.850s 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 33.170s 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 0.730s 0 1 0.00
sram_ctrl_tl_intg_err 3.420s 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 0.730s 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.420s 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 8.844m 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 8.844m 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.910s 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 6.809m 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 6.809m 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 6.809m 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 19.300s 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 4.370s 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 33.170s 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 4.740s 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 4.130s 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 4.130s 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 6.809m 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 0.730s 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 19.300s 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 0.730s 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 0.730s 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 4.130s 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 0.730s 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 5.890s 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets