UART Simulation Results

Monday November 10 2025 16:01:52 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	3.050s		1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.890s		1	1	100.00
V1	csr_rw	uart_csr_rw	0.780s		1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.290s		1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.850s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.010s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.780s		1	1	100.00
		uart_csr_aliasing	0.850s		1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	8.320s		1	1	100.00
V2	parity	uart_smoke	3.050s		1	1	100.00
		uart_tx_rx	8.320s		1	1	100.00
V2	parity_error	uart_intr	8.790s		1	1	100.00
		uart_rx_parity_err	28.870s		1	1	100.00
V2	watermark	uart_tx_rx	8.320s		1	1	100.00
		uart_intr	8.790s		1	1	100.00
V2	fifo_full	uart_fifo_full	11.600s		1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	3.929m		1	1	100.00
V2	fifo_reset	uart_fifo_reset	25.000s		1	1	100.00
V2	rx_frame_err	uart_intr	8.790s		1	1	100.00
V2	rx_break_err	uart_intr	8.790s		1	1	100.00
V2	rx_timeout	uart_intr	8.790s		1	1	100.00
V2	perf	uart_perf	6.389m		1	1	100.00
V2	sys_loopback	uart_loopback	4.890s		1	1	100.00
V2	line_loopback	uart_loopback	4.890s		1	1	100.00
V2	rx_noise_filter	uart_noise_filter	17.670s		1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	28.630s		1	1	100.00
V2	tx_overide	uart_tx_ovrd	12.760s		1	1	100.00
V2	rx_oversample	uart_rx_oversample	24.140s		1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	7.316m		1	1	100.00
V2	stress_all	uart_stress_all	1.099m		1	1	100.00
V2	alert_test	uart_alert_test	0.640s		1	1	100.00
V2	intr_test	uart_intr_test	0.830s		1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.590s		1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.590s		1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.890s		1	1	100.00
		uart_csr_rw	0.780s		1	1	100.00
		uart_csr_aliasing	0.850s		1	1	100.00
		uart_same_csr_outstanding	0.850s		1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.890s		1	1	100.00
		uart_csr_rw	0.780s		1	1	100.00
		uart_csr_aliasing	0.850s		1	1	100.00
		uart_same_csr_outstanding	0.850s		1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.160s		1	1	100.00
		uart_tl_intg_err	1.640s		1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.640s		1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	44.300s		1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00