CHIP Simulation Results

Monday November 10 2025 16:01:52 UTC

GitHub Revision: `3c586cb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.784m	0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.784m	0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.894m	0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.909m	0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.451m	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.451m	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.451m	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	29.140s	0	1	0.00
		chip_sw_example_manufacturer	2.705m	0	1	0.00
		chip_sw_example_concurrency	2.866m	1	1	100.00
		chip_sw_uart_smoketest_signed	10.024s	0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.960s	0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.820s	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.820s	0	1	0.00
V1	xbar_smoke	xbar_smoke	19.810s	1	1	100.00
V1		TOTAL		3	11	27.27
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.138m	0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	35.857m	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.414m	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.647m	0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.222m	0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.735m	0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.086m	0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.420s	0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.420s	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.138m	0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.239m	0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.239m	0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.239m	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	1.808m	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	1.675m	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.043m	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	13.896s	0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.729s	0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	1.558m	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.708m	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	8.124m	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	8.124m	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	9.372s	0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	3.257m	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	3.257m	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.646m	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.621m	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.749m	1	1	100.00
		chip_sw_aes_idle	2.482m	1	1	100.00
		chip_sw_hmac_enc_idle	3.010m	1	1	100.00
		chip_sw_kmac_idle	2.534m	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	2.932m	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	3.047m	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	2.826m	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	2.786m	0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	34.020s	0	1	0.00
		chip_sw_aes_enc_jitter_en	35.620s	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.600s	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.630s	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	37.290s	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.921s	0	1	0.00
		chip_sw_clkmgr_jitter	2.570m	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	5.144m	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	38.800s	0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	37.070s	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	36.340s	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	37.060s	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	42.830s	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	36.760s	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	10.225s	0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.385s	0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.186s	0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.151s	0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.116m	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.897m	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	3.257m	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.316s	0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.897m	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	10.651s	0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	9.353s	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.750s	0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	18.624s	0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	56.411s	0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.116m	0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.043m	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	5.645m	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.048m	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	5.200m	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.311m	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.116m	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	10.039s	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.465s	0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.116m	0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	9.328s	0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	5.200m	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.451s	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.437s	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.257s	0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	9.089s	0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.850s	0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9.450s	0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.465s	0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	14.388s	0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	9.058s	0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	14.388s	0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	14.388s	0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	14.388s	0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	4.541m	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.157s	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	12.489s	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	9.943s	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	58.932s	0	1	0.00
		chip_sw_lc_ctrl_transition	14.388s	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	4.679m	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	12.085m	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.254s	0	1	0.00
		chip_prim_tl_access	8.797m	1	1	100.00
		chip_rv_dm_lc_disabled	1.558m	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.925m	1	1	100.00
		chip_sw_aes_enc_jitter_en	35.620s	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.464m	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.482m	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.014m	1	1	100.00
		chip_sw_hmac_enc_jitter_en	36.600s	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.010m	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.879m	1	1	100.00
		chip_sw_kmac_mode_kmac	3.524m	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	37.290s	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	4.679m	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	14.388s	0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	30.780s	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	3.886m	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.534m	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	5.393m	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	5.393m	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.944s	0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.341m	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	10.139s	0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	4.679m	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.630s	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	38.140m	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	34.020s	0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.749m	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.749m	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.749m	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.894m	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	12.085m	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	12.085m	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.535m	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.921s	0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.254s	0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.116m	0	1	0.00
		chip_sw_data_integrity_escalation	2.239m	0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	14.388s	0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	5.894m	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	4.679m	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	5.535m	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.560m	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	5.894m	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	4.679m	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	5.535m	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.560m	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	14.388s	0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.373s	0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	9.058s	0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.157s	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	12.489s	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	9.943s	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	58.932s	0	1	0.00
		chip_sw_lc_ctrl_transition	14.388s	0	1	0.00
		chip_prim_tl_access	8.797m	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.797m	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	17.521s	0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	13.775s	0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.385s	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	34.020s	0	1	0.00
		chip_sw_aes_enc_jitter_en	35.620s	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.600s	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.630s	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	37.290s	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.921s	0	1	0.00
		chip_sw_clkmgr_jitter	2.570m	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	2.379m	0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	2.379m	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	2.459m	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	2.386m	0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.063m	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	3.770m	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.018m	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.560m	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	5.645m	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	5.645m	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	2.440m	1	1	100.00
		chip_sw_aon_timer_smoketest	2.635m	1	1	100.00
		chip_sw_clkmgr_smoketest	2.092m	1	1	100.00
		chip_sw_csrng_smoketest	2.196m	1	1	100.00
		chip_sw_gpio_smoketest	2.470m	1	1	100.00
		chip_sw_hmac_smoketest	2.735m	1	1	100.00
		chip_sw_kmac_smoketest	2.783m	1	1	100.00
		chip_sw_otbn_smoketest	3.269m	1	1	100.00
		chip_sw_otp_ctrl_smoketest	2.240m	1	1	100.00
		chip_sw_rv_plic_smoketest	2.166m	1	1	100.00
		chip_sw_rv_timer_smoketest	3.201m	1	1	100.00
		chip_sw_rstmgr_smoketest	2.084m	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.171m	1	1	100.00
		chip_sw_uart_smoketest	2.431m	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	9.303s	0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	10.024s	0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.138m	0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	14.000s	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.932m	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.776m	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.630m	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.669m	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	9.900s	0	1	0.00
		chip_rv_dm_lc_disabled	1.558m	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	21.298s	0	1	0.00
		chip_sw_lc_walkthrough_prod	11.327s	0	1	0.00
		chip_sw_lc_walkthrough_prodend	13.751s	0	1	0.00
		chip_sw_lc_walkthrough_rma	43.900s	0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	9.900s	0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	7.601m	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	6.500m	1	1	100.00
		rom_volatile_raw_unlock	9.521s	0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	9.546s	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.179m	0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.025m	0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.654m	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	1.654m	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.820s	0	1	0.00
		chip_same_csr_outstanding	15.270s	0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.820s	0	1	0.00
		chip_same_csr_outstanding	15.270s	0	1	0.00
V2	xbar_base_random_sequence	xbar_random	3.438m	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.960s	1	1	100.00
		xbar_smoke_large_delays	4.973m	1	1	100.00
		xbar_smoke_slow_rsp	5.784m	1	1	100.00
		xbar_random_zero_delays	18.980s	1	1	100.00
		xbar_random_large_delays	6.362m	1	1	100.00
		xbar_random_slow_rsp	35.913m	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	14.610s	1	1	100.00
		xbar_error_and_unmapped_addr	1.434m	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.050m	1	1	100.00
		xbar_error_and_unmapped_addr	1.434m	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.771m	1	1	100.00
		xbar_access_same_device_slow_rsp	45.760m	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.485m	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.602m	1	1	100.00
		xbar_stress_all_with_error	2.424m	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	24.862m	1	1	100.00
		xbar_stress_all_with_reset_error	36.030m	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.845s	0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.233s	0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.009s	0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	9.889s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.327s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	9.933s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.196s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	9.722s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.785s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.913s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.316s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.135s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	9.997s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.228m	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.158m	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.170m	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	57.422s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	57.395s	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.264m	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	55.494s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.244m	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.166m	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.111m	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	1.053m	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	59.671s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	53.003s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	41.662s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	48.276s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.894s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	20.117s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.056s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	10.262s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.614s	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	9.282s	0	1	0.00
		rom_e2e_asm_init_dev	9.235s	0	1	0.00
		rom_e2e_asm_init_prod	11.197s	0	1	0.00
		rom_e2e_asm_init_prod_end	9.141s	0	1	0.00
		rom_e2e_asm_init_rma	11.926s	0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	9.928s	0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.066s	0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.200s	0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.159s	0	1	0.00
V2		TOTAL		67	197	34.01
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.161m	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.492m	1	1	100.00
V2S		TOTAL		2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.977s	0	1	0.00
		rom_e2e_jtag_debug_dev	11.391s	0	1	0.00
		rom_e2e_jtag_debug_rma	9.552s	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.689s	0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.116m	0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.001s	0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	2.925m	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	9.747s	0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	9.914s	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.977s	0	1	0.00
		rom_e2e_jtag_debug_dev	11.391s	0	1	0.00
		rom_e2e_jtag_debug_rma	9.552s	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.926s	0	1	0.00
		rom_e2e_jtag_inject_dev	12.980s	0	1	0.00
		rom_e2e_jtag_inject_rma	13.030s	0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.001s	0	1	0.00
V3		TOTAL		0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	14.439m	0	1	0.00
		chip_sw_entropy_src_kat_test	2.704m	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.418m	1	1	100.00
		chip_plic_all_irqs_0	6.778m	1	1	100.00
		chip_plic_all_irqs_10	5.777m	1	1	100.00
		chip_sw_dma_inline_hashing	3.054m	1	1	100.00
		chip_sw_dma_abort	2.588m	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	9.875s	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.237s	0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	9.912s	0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	9.991s	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.123s	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	9.602s	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.015s	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	9.611s	0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	9.739s	0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	9.811s	0	1	0.00
		chip_sw_entropy_src_smoketest	3.009m	1	1	100.00
		chip_sw_mbx_smoketest	3.815m	1	1	100.00
		TOTAL		79	241	32.78

Failure Buckets

Job returned non-zero exit code has 122 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.63554035198772176892293376687608203914678272681286211142219443696459073571184
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 153.233s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.23509004358480072126460079147537572505750485947935809595032975204022626244668
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 125.731s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.19890440966770027035900928775288852868167748134925950708526248504367120382915
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 119.698s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.38992085950901999606712267186614790448182343540113196043681158477075456551237
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 125.535s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.51476293460892238316177220164805991606538314027871960601191908282901860125954
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 158.398s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 117 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 11 failures:
- Test chip_sw_otbn_ecdsa_op_irq_jitter_en has 1 failures.
  - 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.31230146960874571083836386258677357921755890601766206099493693732700465102091
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.59811438400102823507054950573816488791670661589180467491728789526922189280908
    Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.107662812216009825799188037003971473463736844441862867023669406541367453807026
    Line 414, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.60955292880429577221127184576443690403945811610103749635924888778758014915363
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.50407408143503524943777488962243802316804595089685129083955407863315281691751
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 6 failures:
- Test chip_sw_rstmgr_cpu_info has 1 failures.
  - 0.chip_sw_rstmgr_cpu_info.63238867755454653485350559947273245492593662824510591678796542844416090542419
    Line 486, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 375.248000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 375.248000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_soc_proxy_smoketest has 1 failures.
  - 0.chip_sw_soc_proxy_smoketest.78271528512500369374177872082085515689340234322263596175441584708144971400027
    Line 452, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
```
      Offending '((!rstreqs[1]) && (reset_cause != HwReq))'
  UVM_ERROR @ 143.504000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 143.504000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_aes_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_aes_trans.64330581164519355255478856181505211444705522223198918909682595858898973676525
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_hmac_trans.527450130977397596802696478764650892965032293828493522424340251807148693532
    Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_kmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_kmac_trans.23590950972637051666856064306968905374031429771734768411446554977958021373915
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 1 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.39783841028080846281692072774722212207038859810162156662802788916489311690515
    Line 138, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.7467799439398830797334766135789215227931231315124476834895119157484430266840
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.26493033836285147267481587203315409626628674997979227906373690060817857092291
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 2 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.41810318459291385288720655377982423839374804740719838678336997307693726299519
    Line 511, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 905.702000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
  UVM_INFO @ 905.702000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.
  - 0.chip_sw_rstmgr_rst_cnsty_escalation.43330129081099172122012832756713532747625671241819439552143280322157558685189
    Line 470, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
```
  UVM_ERROR @ 905.755000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
  UVM_INFO @ 905.755000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.31570825833016133340410867087198269737417250954982199035662073320946684357170
Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 268.203000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1551503240747587390743325491718388011106995547331687689762364361934118785096919183523185868477792356347145886076058407485839051474435655547236037295430748 [0x1d9f9701aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd39bc927f07f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 268.203000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.75613647820871999491208610161034822240633954919241172783031207238068769181905
Line 432, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 268.111000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (10631352598642231213650243838959556014904451509586763423009114199092565642098962667386340924896714342943369831576520061831063919426000012745075220172594268 [0xcafcf812aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd34caa48e37f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 268.111000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42095) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.33560426667626880284788821732394839425489814351795302895196210042942147203505
Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 117.012000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42095) { a_addr: 'h30480000  a_data: 'hb80054b3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h0  a_user: 'h26907  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 117.012000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.24373852359439361105767059659971989879120537739494277061396352834411728674079
Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 116.997000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42095) { a_addr: 'h30480000  a_data: 'hab80bb31  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2d  a_opcode: 'h0  a_user: 'h2693f  d_param: 'h0  d_source: 'h2d  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 116.997000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.22090463012936315980108491184123991101235476673278238435120423086730525546520
    Line 618, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.82015561411280232083551279574493561609685776101329510625063520369499226585006
    Line 437, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 214.845000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 214.845000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.31989829382790218072602062562536015218956633940196794309478681383995432408520
    Line 520, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 158.192000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 158.192000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.4109932016375114917335069686652141365480842056971776995532342642478655262473
    Line 491, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 290.013000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
  UVM_INFO @ 290.013000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.3720156537035900659136640707654868317763512113304350166219066705115190068011
    Line 414, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 138.792000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 138.792000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns * has 1 failures:
- Test chip_sw_soc_proxy_gpios has 1 failures.
  - 0.chip_sw_soc_proxy_gpios.63187545549834296832773718054257955021002755376335555263511405513538280615903
    Line 426, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log
```
  UVM_ERROR @ 136.505000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
  UVM_INFO @ 136.505000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 1 failures:
- Test chip_sw_aon_timer_irq has 1 failures.
  - 0.chip_sw_aon_timer_irq.58193772972926266345024296473347757481118859363421647726071136257750049896890
    Line 425, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
```
  UVM_ERROR @ 575.561000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4356 usec which is not in the range 398 usec and 453 usec
  UVM_INFO @ 575.561000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.301365439061432326846794883522835155314994911829039834899130308910896377465
    Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 164.341000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 164.341000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.1942966457826699683455738947545371478921084439061626932865813539781146493309
    Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 251.602000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 251.602000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.11461842962107872909316553467296996410348492506490661401437232410541597645408
    Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.12032002469098840386688924381420427023725919043763087639915130014271286719640
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 117.714000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 117.714000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.45774716307013486691798679821235993349292109531846406878768950068094751724704
    Line 217, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 128.375000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x407ec read out mismatch
  UVM_INFO @ 128.375000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.106969909507793341071284398173469419429635847733522542191426823387701252543603
    Line 283, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.198696778867105095262434034963697029002777625984430822716020457134479882635
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 159.392000 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 159.392000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```