MBX Simulation Results

Tuesday November 11 2025 16:10:56 UTC

GitHub Revision: b700cc2

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	81.0	8424.443603	1	1	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	2.0	62.93992	1	1	100.00
V1	csr_rw	mbx_csr_rw	2.0	28.669014	1	1	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	3.0	69.365431	1	1	100.00
V1	csr_aliasing	mbx_csr_aliasing	2.0	21.393280999999998	1	1	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	2.0	29.696189999999998	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	2.0	28.669014	1	1	100.00
		mbx_csr_aliasing	2.0	21.393280999999998	1	1	100.00
V1		TOTAL			6	6	100.00
V2	mbx_stress	mbx_stress	68.0	11303.592002000001	1	1	100.00
V2	mbx_max_activity	mbx_stress_zero_delays	9.0	40.328364	0	1	0.00
V2	mbx_imbx_oob	mbx_imbx_oob	17.0	1514.2141029999998	1	1	100.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	21.0	564.384895	1	1	100.00
V2	alert_test	mbx_alert_test	1.0	15.096794	1	1	100.00
V2	intr_test	mbx_intr_test	1.0	17.03705	1	1	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	4.0	230.823529	1	1	100.00
V2	tl_d_illegal_access	mbx_tl_errors	4.0	230.823529	1	1	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	2.0	62.93992	1	1	100.00
		mbx_csr_rw	2.0	28.669014	1	1	100.00
		mbx_csr_aliasing	2.0	21.393280999999998	1	1	100.00
		mbx_same_csr_outstanding	2.0	96.388408	1	1	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	2.0	62.93992	1	1	100.00
		mbx_csr_rw	2.0	28.669014	1	1	100.00
		mbx_csr_aliasing	2.0	21.393280999999998	1	1	100.00
		mbx_same_csr_outstanding	2.0	96.388408	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	mbx_sec_cm	1.0	22.001322000000002	1	1	100.00
		mbx_tl_intg_err	2.0	420.73885600000006	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	i2c_host_smoke	36.82	0.0	1	1	100.00
		i2c_host_override	0.74	0.0	1	1	100.00
		i2c_host_fifo_watermark	95.75	0.0	1	1	100.00
		i2c_host_fifo_overflow	55.09	0.0	1	1	100.00
		i2c_host_fifo_reset_fmt	1.05	0.0	1	1	100.00
		i2c_host_fifo_fmt_empty	4.46	0.0	1	1	100.00
		i2c_host_fifo_reset_rx	6.47	0.0	1	1	100.00
		i2c_host_fifo_full	106.35	0.0	1	1	100.00
		i2c_host_perf	233.11	0.0	1	1	100.00
		i2c_host_perf_precise	1.76	0.0	1	1	100.00
		i2c_host_stretch_timeout	6.95	0.0	1	1	100.00
		i2c_host_error_intr	1.3	0.0	0	1	0.00
		i2c_host_stress_all	120.28	0.0	0	1	0.00
		i2c_target_glitch	2.15	0.0	0	1	0.00
		i2c_target_smoke	16.81	0.0	1	1	100.00
		i2c_target_stress_wr	20.46	0.0	1	1	100.00
		i2c_target_stress_rd	3.91	0.0	1	1	100.00
		i2c_target_stretch	9.69	0.0	1	1	100.00
		i2c_target_intr_smoke	5.06	0.0	1	1	100.00
		i2c_target_intr_stress_wr	87.36	0.0	1	1	100.00
		i2c_target_timeout	5.32	0.0	1	1	100.00
		i2c_target_unexp_stop	1.47	0.0	0	1	0.00
		i2c_target_fifo_reset_acq	1.09	0.0	1	1	100.00
		i2c_target_fifo_reset_tx	1.17	0.0	1	1	100.00
		i2c_target_perf	4.05	0.0	1	1	100.00
		i2c_target_stress_all	21.94	0.0	1	1	100.00
		i2c_target_bad_addr	3.23	0.0	1	1	100.00
		i2c_target_hrst	18.29	0.0	0	1	0.00
		i2c_host_stress_all_with_rand_reset	14.4	0.0	0	1	0.00
		i2c_target_stress_all_with_rand_reset	24.87	0.0	0	1	0.00
		i2c_host_mode_toggle	0.94	0.0	1	1	100.00
		i2c_host_may_nack	13.65	0.0	1	1	100.00
		i2c_target_fifo_watermarks_acq	1.78	0.0	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.7	0.0	1	1	100.00
		i2c_target_tx_stretch_ctrl	2.01	0.0	1	1	100.00
		i2c_target_smbus_maxlen	1.66	0.0	1	1	100.00
		i2c_target_nack_acqfull	1.75	0.0	1	1	100.00
		i2c_target_nack_acqfull_addr	1.64	0.0	1	1	100.00
		i2c_target_nack_txstretch	1.04	0.0	1	1	100.00
		i2c_sec_cm	0.81	0.0	1	1	100.00
		i2c_alert_test	0.64	0.0	1	1	100.00
		i2c_tl_errors	1.09	0.0	1	1	100.00
		i2c_tl_intg_err	1.7	0.0	1	1	100.00
		i2c_intr_test	0.63	0.0	1	1	100.00
		i2c_csr_hw_reset	0.67	0.0	1	1	100.00
		i2c_csr_rw	0.73	0.0	1	1	100.00
		i2c_csr_bit_bash	3.32	0.0	1	1	100.00
		i2c_csr_aliasing	1.13	0.0	1	1	100.00
		i2c_same_csr_outstanding	0.75	0.0	1	1	100.00
		i2c_csr_mem_rw_with_rand_reset	0.82	0.0	1	1	100.00
		rv_dm_csr_aliasing	45.92	0.0	1	1	100.00
		rv_dm_jtag_dtm_csr_hw_reset	1.23	0.0	1	1	100.00
		rv_dm_jtag_dtm_csr_rw	0.96	0.0	1	1	100.00
		rv_dm_jtag_dtm_csr_bit_bash	5.62	0.0	1	1	100.00
		rv_dm_jtag_dtm_csr_aliasing	1.17	0.0	1	1	100.00
		rv_dm_jtag_dmi_csr_hw_reset	5.38	0.0	1	1	100.00
		rv_dm_jtag_dmi_csr_rw	1.7	0.0	1	1	100.00
		rv_dm_jtag_dmi_csr_bit_bash	1.82	0.0	1	1	100.00
		rv_dm_jtag_dmi_csr_aliasing	34.62	0.0	1	1	100.00
		rv_dm_tap_fsm_rand_reset	0.7	0.0	0	1	0.00
		rv_dm_tl_errors	0.62	0.0	0	1	0.00
		rv_dm_tl_intg_err	6.92	0.0	1	1	100.00
		rv_dm_mem_walk	0.62	0.0	1	1	100.00
		rv_dm_mem_partial_access	0.67	0.0	1	1	100.00
		rv_dm_csr_hw_reset	1.31	0.0	1	1	100.00
		rv_dm_csr_rw	1.21	0.0	1	1	100.00
		rv_dm_csr_bit_bash	18.79	0.0	1	1	100.00
		rv_dm_same_csr_outstanding	4.74	0.0	1	1	100.00
		rv_dm_csr_mem_rw_with_rand_reset	0.7	0.0	0	1	0.00
		rv_dm_smoke	9.79	0.0	1	1	100.00
		rv_dm_tap_fsm	7.06	0.0	1	1	100.00
		rv_dm_sba_tl_access	488.53999999999996	0.0	0	1	0.00
		rv_dm_delayed_resp_sba_tl_access	257.0	0.0	0	1	0.00
		rv_dm_bad_sba_tl_access	236.26	0.0	0	1	0.00
		rv_dm_autoincr_sba_tl_access	254.36	0.0	0	1	0.00
		rv_dm_cmderr_busy	0.77	0.0	1	1	100.00
		rv_dm_cmderr_not_supported	1.92	0.0	1	1	100.00
		rv_dm_cmderr_exception	1.11	0.0	1	1	100.00
		rv_dm_mem_tl_access_halted	1.26	0.0	1	1	100.00
		rv_dm_mem_tl_access_resuming	1.17	0.0	0	1	0.00
		rv_dm_hart_unavail	0.76	0.0	0	1	0.00
		rv_dm_cmderr_halt_resume	1.21	0.0	1	1	100.00
		rv_dm_dataaddr_rw_access	0.88	0.0	1	1	100.00
		rv_dm_halt_resume_whereto	2.87	0.0	1	1	100.00
		rv_dm_sba_debug_disabled	3.97	0.0	1	1	100.00
		rv_dm_ndmreset_req	1.1	0.0	1	1	100.00
		rv_dm_jtag_dtm_idle_hint	1.09	0.0	1	1	100.00
		rv_dm_jtag_dmi_dm_inactive	1.95	0.0	1	1	100.00
		rv_dm_jtag_dmi_debug_disabled	1.71	0.0	0	1	0.00
		rv_dm_jtag_dtm_hard_reset	1.83	0.0	1	1	100.00
		rv_dm_abstractcmd_status	1.02	0.0	1	1	100.00
		rv_dm_rom_read_access	0.72	0.0	1	1	100.00
		rv_dm_progbuf_read_write_execute	0.87	0.0	1	1	100.00
		rv_dm_debug_disabled	0.98	0.0	1	1	100.00
		rv_dm_dmi_failed_op	0.88	0.0	1	1	100.00
		rv_dm_hartsel_warl	1.24	0.0	1	1	100.00
		rv_dm_buffered_enable	0.88	0.0	1	1	100.00
		rv_dm_sparse_lc_gate_fsm	0.9	0.0	1	1	100.00
		rv_dm_scanmode	564.37	0.0	0	1	0.00
		rv_dm_stress_all	2.44	0.0	0	1	0.00
		rv_dm_stress_all_with_rand_reset	0.66	0.0	0	1	0.00
		rv_dm_sec_cm	0.88	0.0	1	1	100.00
		rv_dm_alert_test	0.68	0.0	1	1	100.00
		hmac_smoke	8.98	0.0	1	1	100.00
		hmac_long_msg	19.49	0.0	1	1	100.00
		hmac_stress_reset	1.04	0.0	1	1	100.00
		hmac_back_pressure	2.52	0.0	1	1	100.00
		hmac_datapath_stress	1029.16	0.0	1	1	100.00
		hmac_burst_wr	0.68	0.0	1	1	100.00
		hmac_error	34.34	0.0	1	1	100.00
		hmac_wipe_secret	85.34	0.0	1	1	100.00
		hmac_test_sha256_vectors	7.63	0.0	1	1	100.00
		hmac_test_sha384_vectors	18.97	0.0	1	1	100.00
		hmac_test_sha512_vectors	383.74	0.0	1	1	100.00
		hmac_test_hmac256_vectors	6.04	0.0	1	1	100.00
		hmac_test_hmac384_vectors	7.75	0.0	1	1	100.00
		hmac_test_hmac512_vectors	11.91	0.0	1	1	100.00
		hmac_stress_all	793.94	0.0	1	1	100.00
		hmac_stress_all_with_rand_reset	96.42	0.0	1	1	100.00
		hmac_directed	4.53	0.0	1	1	100.00
		hmac_sec_cm	0.89	0.0	1	1	100.00
		hmac_alert_test	0.59	0.0	1	1	100.00
		hmac_tl_errors	1.45	0.0	1	1	100.00
		hmac_tl_intg_err	2.36	0.0	1	1	100.00
		hmac_intr_test	0.53	0.0	1	1	100.00
		hmac_csr_hw_reset	0.75	0.0	1	1	100.00
		hmac_csr_rw	0.82	0.0	1	1	100.00
		hmac_csr_bit_bash	3.56	0.0	1	1	100.00
		hmac_csr_aliasing	2.34	0.0	1	1	100.00
		hmac_same_csr_outstanding	1.41	0.0	1	1	100.00
		hmac_csr_mem_rw_with_rand_reset	0.97	0.0	1	1	100.00
		xbar_smoke	9.92	0.0	5	5	100.00
		xbar_smoke_zero_delays	8.75	0.0	5	5	100.00
		xbar_smoke_large_delays	274.24	0.0	5	5	100.00
		xbar_smoke_slow_rsp	387.16	0.0	5	5	100.00
		xbar_random	228.27	0.0	5	5	100.00
		xbar_random_zero_delays	52.49	0.0	5	5	100.00
		xbar_random_large_delays	1673.35	0.0	5	5	100.00
		xbar_random_slow_rsp	229.2	0.0	5	5	100.00
		xbar_access_same_device	175.25	0.0	5	5	100.00
		xbar_access_same_device_slow_rsp	3121.56	0.0	5	5	100.00
		xbar_same_source	109.43	0.0	5	5	100.00
		xbar_error_random	96.35	0.0	5	5	100.00
		xbar_unmapped_addr	62.06	0.0	5	5	100.00
		xbar_error_and_unmapped_addr	72.36	0.0	5	5	100.00
		xbar_stress_all	1317.07	0.0	5	5	100.00
		xbar_stress_all_with_rand_reset	1237.36	0.0	5	5	100.00
		xbar_stress_all_with_error	51.26	0.0	5	5	100.00
		xbar_stress_all_with_reset_error	803.02	0.0	5	5	100.00
		aon_timer_smoke	0.73	0.0	1	1	100.00
		aon_timer_prescaler	3.22	0.0	1	1	100.00
		aon_timer_jump	1.0	0.0	1	1	100.00
		aon_timer_custom_intr	0.89	0.0	1	1	100.00
		aon_timer_smoke_max_thold	1.26	0.0	1	1	100.00
		aon_timer_smoke_min_thold	0.94	0.0	1	1	100.00
		aon_timer_wkup_count_cdc_hi	1.06	0.0	1	1	100.00
		aon_timer_alternating_enable_on_off	10.07	0.0	1	1	100.00
		aon_timer_stress_all_with_rand_reset	13.77	0.0	1	1	100.00
		aon_timer_stress_all	25.21	0.0	1	1	100.00
		aon_timer_sec_cm	5.4	0.0	1	1	100.00
		aon_timer_alert_test	0.68	0.0	1	1	100.00
		aon_timer_tl_errors	1.02	0.0	1	1	100.00
		aon_timer_tl_intg_err	2.95	0.0	1	1	100.00
		aon_timer_intr_test	0.89	0.0	1	1	100.00
		aon_timer_mem_walk	0.85	0.0	1	1	100.00
		aon_timer_mem_partial_access	1.16	0.0	1	1	100.00
		aon_timer_csr_hw_reset	1.24	0.0	1	1	100.00
		aon_timer_csr_rw	0.83	0.0	1	1	100.00
		aon_timer_csr_bit_bash	3.75	0.0	1	1	100.00
		aon_timer_csr_aliasing	1.12	0.0	1	1	100.00
		aon_timer_same_csr_outstanding	3.6	0.0	1	1	100.00
		aon_timer_csr_mem_rw_with_rand_reset	0.96	0.0	1	1	100.00
		gpio_smoke	0.84	0.0	1	1	100.00
		gpio_smoke_no_pullup_pulldown	0.77	0.0	1	1	100.00
		gpio_inp_prd_cnt	0.64	0.0	1	1	100.00
		gpio_random_dout_din	0.74	0.0	1	1	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.03	0.0	1	1	100.00
		gpio_dout_din_regs_random_rw	0.64	0.0	1	1	100.00
		gpio_intr_rand_pgm	0.93	0.0	1	1	100.00
		gpio_rand_intr_trigger	0.92	0.0	1	1	100.00
		gpio_intr_with_filter_rand_intr_event	1.24	0.0	1	1	100.00
		gpio_filter_stress	17.04	0.0	1	1	100.00
		gpio_random_long_reg_writes_reg_reads	3.57	0.0	1	1	100.00
		gpio_full_random	0.72	0.0	1	1	100.00
		gpio_stress_all	79.57	0.0	1	1	100.00
		gpio_stress_all_with_rand_reset	9.17	0.0	0	1	0.00
		gpio_rand_straps	0.59	0.0	1	1	100.00
		gpio_sec_cm	0.87	0.0	1	1	100.00
		gpio_alert_test	0.62	0.0	1	1	100.00
		gpio_csr_rw	0.73	0.0	1	1	100.00
		gpio_same_csr_outstanding	0.83	0.0	0	1	0.00
		gpio_csr_aliasing	1.45	0.0	1	1	100.00
		gpio_csr_mem_rw_with_rand_reset	0.96	0.0	1	1	100.00
		gpio_tl_intg_err	1.71	0.0	1	1	100.00
		gpio_tl_errors	1.12	0.0	1	1	100.00
		gpio_intr_test	0.62	0.0	1	1	100.00
		gpio_csr_hw_reset	0.69	0.0	1	1	100.00
		gpio_csr_bit_bash	2.31	0.0	1	1	100.00
		gpio_smoke_en_cdc_prim	1.14	0.0	1	1	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	0.93	0.0	1	1	100.00
		tl_agent_smoke	1.06	0.0	1	1	100.00
		spi_device_csb_read	0.78	0.0	1	1	100.00
		spi_device_mem_parity	0.66	0.0	0	1	0.00
		spi_device_ram_cfg	0.66	0.0	0	1	0.00
		spi_device_tpm_read_hw_reg	7.38	0.0	1	1	100.00
		spi_device_tpm_all	14.33	0.0	1	1	100.00
		spi_device_tpm_sts_read	0.64	0.0	1	1	100.00
		spi_device_tpm_rw	0.87	0.0	1	1	100.00
		spi_device_pass_cmd_filtering	8.56	0.0	1	1	100.00
		spi_device_pass_addr_payload_swap	3.49	0.0	1	1	100.00
		spi_device_intercept	15.58	0.0	1	1	100.00
		spi_device_mailbox	2.63	0.0	1	1	100.00
		spi_device_upload	2.0	0.0	1	1	100.00
		spi_device_cfg_cmd	6.59	0.0	1	1	100.00
		spi_device_flash_mode	3.36	0.0	1	1	100.00
		spi_device_flash_mode_ignore_cmds	27.87	0.0	1	1	100.00
		spi_device_read_buffer_direct	4.95	0.0	1	1	100.00
		spi_device_flash_all	78.91	0.0	1	1	100.00
		spi_device_flash_and_tpm	166.48	0.0	1	1	100.00
		spi_device_flash_and_tpm_min_idle	182.3	0.0	1	1	100.00
		spi_device_stress_all	0.87	0.0	1	1	100.00
		spi_device_sec_cm	1.23	0.0	1	1	100.00
		spi_device_alert_test	0.71	0.0	1	1	100.00
		spi_device_tl_errors	1.3	0.0	1	1	100.00
		spi_device_tl_intg_err	11.03	0.0	1	1	100.00
		spi_device_intr_test	0.79	0.0	1	1	100.00
		spi_device_mem_walk	0.84	0.0	1	1	100.00
		spi_device_mem_partial_access	1.88	0.0	1	1	100.00
		spi_device_csr_hw_reset	1.18	0.0	1	1	100.00
		spi_device_csr_rw	1.29	0.0	1	1	100.00
		spi_device_csr_bit_bash	15.95	0.0	1	1	100.00
		spi_device_csr_aliasing	9.89	0.0	1	1	100.00
		spi_device_same_csr_outstanding	3.27	0.0	1	1	100.00
		spi_device_csr_mem_rw_with_rand_reset	1.35	0.0	1	1	100.00
		clkmgr_smoke	0.96	0.0	1	1	100.00
		clkmgr_frequency	0.68	0.0	0	1	0.00
		clkmgr_frequency_timeout	0.66	0.0	0	1	0.00
		clkmgr_peri	0.76	0.0	1	1	100.00
		clkmgr_trans	0.94	0.0	1	1	100.00
		clkmgr_clk_status	0.73	0.0	1	1	100.00
		clkmgr_idle_intersig_mubi	1.57	0.0	1	1	100.00
		clkmgr_regwen	0.66	0.0	0	1	0.00
		clkmgr_sec_cm	14.31	0.0	1	1	100.00
		clkmgr_stress_all_with_rand_reset	1.07	0.0	0	1	0.00
		clkmgr_stress_all	1.68	0.0	0	1	0.00
		clkmgr_alert_test	0.88	0.0	1	1	100.00
		clkmgr_shadow_reg_errors	1.12	0.0	1	1	100.00
		clkmgr_shadow_reg_errors_with_csr_rw	0.72	0.0	0	1	0.00
		clkmgr_tl_errors	1.19	0.0	1	1	100.00
		clkmgr_tl_intg_err	0.76	0.0	0	1	0.00
		clkmgr_csr_hw_reset	0.88	0.0	1	1	100.00
		clkmgr_csr_rw	0.78	0.0	1	1	100.00
		clkmgr_csr_bit_bash	2.63	0.0	0	1	0.00
		clkmgr_csr_aliasing	1.64	0.0	1	1	100.00
		clkmgr_same_csr_outstanding	0.69	0.0	0	1	0.00
		clkmgr_csr_mem_rw_with_rand_reset	0.93	0.0	0	1	0.00
		prim_async_alert	0.46	0.0	1	1	100.00
		prim_async_fatal_alert	0.46	0.0	1	1	100.00
		prim_async_fatal_alert_with_3_cycles_skew	0.53	0.0	1	1	100.00
		prim_sync_alert	0.58	0.0	1	1	100.00
		prim_sync_fatal_alert	0.47	0.0	1	1	100.00
		rstmgr_cnsty_chk_test	2.11	0.0	1	1	100.00
		sram_ctrl_smoke	54.93	0.0	2	2	100.00
		sram_ctrl_multiple_keys	747.01	0.0	2	2	100.00
		sram_ctrl_bijection	2133.47	0.0	2	2	100.00
		sram_ctrl_stress_pipeline	261.14	0.0	2	2	100.00
		sram_ctrl_partial_access	17.28	0.0	2	2	100.00
		sram_ctrl_partial_access_b2b	278.78	0.0	2	2	100.00
		sram_ctrl_max_throughput	23.22	0.0	2	2	100.00
		sram_ctrl_throughput_w_partial_write	24.11	0.0	2	2	100.00
		sram_ctrl_throughput_w_readback	33.92	0.0	2	2	100.00
		sram_ctrl_lc_escalation	52.93	0.0	2	2	100.00
		sram_ctrl_access_during_key_req	1079.6	0.0	2	2	100.00
		sram_ctrl_executable	607.87	0.0	2	2	100.00
		sram_ctrl_regwen	748.31	0.0	2	2	100.00
		sram_ctrl_ram_cfg	2.96	0.0	2	2	100.00
		sram_ctrl_mem_walk	127.64000000000001	0.0	2	2	100.00
		sram_ctrl_mem_partial_access	53.87	0.0	2	2	100.00
		sram_ctrl_readback_err	3.95	0.0	1	2	50.00
		sram_ctrl_mubi_enc_err	4.04	0.0	2	2	100.00
		sram_ctrl_stress_all_with_rand_reset	70.82	0.0	2	2	100.00
		sram_ctrl_stress_all	1710.54	0.0	2	2	100.00
		sram_ctrl_sec_cm	0.77	0.0	0	2	0.00
		sram_ctrl_alert_test	0.96	0.0	2	2	100.00
		sram_ctrl_passthru_mem_tl_intg_err	33.11	0.0	2	2	100.00
		sram_ctrl_tl_errors	1.92	0.0	2	2	100.00
		sram_ctrl_tl_intg_err	2.53	0.0	2	2	100.00
		sram_ctrl_csr_hw_reset	0.75	0.0	2	2	100.00
		sram_ctrl_csr_rw	0.67	0.0	2	2	100.00
		sram_ctrl_csr_bit_bash	1.79	0.0	2	2	100.00
		sram_ctrl_csr_aliasing	0.69	0.0	2	2	100.00
		sram_ctrl_same_csr_outstanding	0.97	0.0	2	2	100.00
		sram_ctrl_csr_mem_rw_with_rand_reset	2.71	0.0	2	2	100.00
		uart_smoke	3.3	0.0	1	1	100.00
		uart_tx_rx	30.24	0.0	1	1	100.00
		uart_fifo_full	15.21	0.0	1	1	100.00
		uart_fifo_overflow	91.06	0.0	1	1	100.00
		uart_fifo_reset	57.3	0.0	1	1	100.00
		uart_rx_oversample	7.38	0.0	1	1	100.00
		uart_intr	13.76	0.0	1	1	100.00
		uart_noise_filter	2.96	0.0	0	1	0.00
		uart_rx_start_bit_filter	1.92	0.0	1	1	100.00
		uart_rx_parity_err	235.8	0.0	1	1	100.00
		uart_tx_ovrd	2.78	0.0	1	1	100.00
		uart_loopback	3.11	0.0	1	1	100.00
		uart_perf	686.4	0.0	1	1	100.00
		uart_long_xfer_wo_dly	87.8	0.0	1	1	100.00
		uart_stress_all_with_rand_reset	17.3	0.0	1	1	100.00
		uart_stress_all	619.54	0.0	1	1	100.00
		uart_sec_cm	0.88	0.0	1	1	100.00
		uart_alert_test	0.66	0.0	1	1	100.00
		uart_tl_errors	1.64	0.0	1	1	100.00
		uart_tl_intg_err	1.41	0.0	1	1	100.00
		uart_intr_test	0.71	0.0	1	1	100.00
		uart_csr_hw_reset	0.71	0.0	1	1	100.00
		uart_csr_rw	0.61	0.0	1	1	100.00
		uart_csr_bit_bash	1.26	0.0	1	1	100.00
		uart_csr_aliasing	0.76	0.0	1	1	100.00
		uart_same_csr_outstanding	0.74	0.0	1	1	100.00
		uart_csr_mem_rw_with_rand_reset	0.73	0.0	1	1	100.00
		kmac_smoke	29.2	0.0	2	2	100.00
		kmac_long_msg_and_output	2360.83	0.0	2	2	100.00
		kmac_sideload	216.44	0.0	2	2	100.00
		kmac_sideload_invalid	4.05	0.0	2	2	100.00
		kmac_burst_write	897.06	0.0	2	2	100.00
		kmac_test_vectors_sha3_224	35.76	0.0	2	2	100.00
		kmac_test_vectors_sha3_256	1701.54	0.0	2	2	100.00
		kmac_test_vectors_sha3_384	21.12	0.0	2	2	100.00
		kmac_test_vectors_sha3_512	820.86	0.0	2	2	100.00
		kmac_test_vectors_shake_128	158.5	0.0	2	2	100.00
		kmac_test_vectors_shake_256	1893.78	0.0	2	2	100.00
		kmac_test_vectors_kmac	2.6	0.0	2	2	100.00
		kmac_test_vectors_kmac_xof	3.07	0.0	2	2	100.00
		kmac_app	212.32	0.0	2	2	100.00
		kmac_app_with_partial_data	110.99	0.0	2	2	100.00
		kmac_entropy_refresh	206.47	0.0	2	2	100.00
		kmac_mubi	323.87	0.0	2	2	100.00
		kmac_error	106.43	0.0	2	2	100.00
		kmac_key_error	7.29	0.0	2	2	100.00
		kmac_edn_timeout_error	3.33	0.0	2	2	100.00
		kmac_entropy_mode_error	23.45	0.0	2	2	100.00
		kmac_entropy_ready_error	28.23	0.0	2	2	100.00
		kmac_lc_escalation	1.57	0.0	2	2	100.00
		kmac_stress_all	496.3	0.0	2	2	100.00
		kmac_stress_all_with_rand_reset	86.54	0.0	2	2	100.00
		kmac_sec_cm	61.599999999999994	0.0	2	2	100.00
		kmac_alert_test	1.02	0.0	2	2	100.00
		kmac_shadow_reg_errors	1.89	0.0	2	2	100.00
		kmac_shadow_reg_errors_with_csr_rw	3.39	0.0	2	2	100.00
		kmac_mem_walk	0.83	0.0	2	2	100.00
		kmac_mem_partial_access	1.37	0.0	2	2	100.00
		kmac_tl_errors	2.62	0.0	2	2	100.00
		kmac_tl_intg_err	3.5	0.0	2	2	100.00
		kmac_intr_test	0.94	0.0	2	2	100.00
		kmac_csr_hw_reset	1.32	0.0	2	2	100.00
		kmac_csr_rw	1.08	0.0	2	2	100.00
		kmac_csr_bit_bash	6.56	0.0	2	2	100.00
		kmac_csr_aliasing	6.34	0.0	2	2	100.00
		kmac_same_csr_outstanding	2.72	0.0	2	2	100.00
		kmac_csr_mem_rw_with_rand_reset	1.96	0.0	2	2	100.00
		prim_lfsr_gal_smoke	1.22	0.0	1	1	100.00
		prim_lfsr_fib_smoke	1.66	0.0	1	1	100.00
		prim_present_test	20.77	0.0	1	1	100.00
		prim_prince_test	27.08	0.0	1	1	100.00
		spi_host_smoke	23.0	4193.254409	1	1	100.00
		spi_host_speed	5.0	183.956358	1	1	100.00
		spi_host_upper_range_clkdiv	124.00000000000001	3447.813328	1	1	100.00
		spi_host_performance	1.0	20.532577	1	1	100.00
		spi_host_sw_reset	10.0	492.266491	1	1	100.00
		spi_host_overflow_underflow	3.0	205.51031400000002	1	1	100.00
		spi_host_error_cmd	2.0	30.06473	1	1	100.00
		spi_host_event	53.0	11721.718413	1	1	100.00
		spi_host_passthrough_mode	2.0	70.622709	1	1	100.00
		spi_host_status_stall	39.0	52354.758318	1	1	100.00
		spi_host_idlecsbactive	2.0	112.956096	1	1	100.00
		spi_host_stress_all	12.0	1217.506068	1	1	100.00
		spi_host_spien	99.0	4332.119369	1	1	100.00
		spi_host_sec_cm	1.0	210.41936900000002	1	1	100.00
		spi_host_alert_test	2.0	48.940404	1	1	100.00
		spi_host_tl_errors	3.0	269.084427	1	1	100.00
		spi_host_tl_intg_err	2.0	906.099635	1	1	100.00
		spi_host_intr_test	1.0	23.350882000000002	1	1	100.00
		spi_host_mem_walk	1.0	21.224335	1	1	100.00
		spi_host_mem_partial_access	1.0	29.831575	1	1	100.00
		spi_host_csr_hw_reset	1.0	25.703343	1	1	100.00
		spi_host_csr_rw	2.0	28.268094	1	1	100.00
		spi_host_csr_bit_bash	3.0	806.2960400000001	1	1	100.00
		spi_host_csr_aliasing	2.0	22.089192999999998	1	1	100.00
		spi_host_same_csr_outstanding	2.0	25.735337	1	1	100.00
		spi_host_csr_mem_rw_with_rand_reset	2.0	58.950548000000005	1	1	100.00
		ac_range_check_smoke	29.0	6340.722522	1	1	100.00
		ac_range_check_smoke_racl	45.0	6991.636254	1	1	100.00
		ac_range_check_smoke_high_threshold	26.0	1148.055809	1	1	100.00
		ac_range_check_bypass	31.0	1316.4341729999999	1	1	100.00
		ac_range_check_lock_range	4.0	232.00931899999998	1	1	100.00
		ac_range_check_stress_all_with_rand_reset	208.0	10584.427973	1	1	100.00
		ac_range_check_stress_all	147.0	2670.0795780000003	0	1	0.00
		ac_range_check_sec_cm	2.0	12.678741	1	1	100.00
		ac_range_check_alert_test	2.0	49.490661	1	1	100.00
		ac_range_check_tl_errors	3.0	153.34707500000002	1	1	100.00
		ac_range_check_tl_intg_err	9.0	1191.488051	1	1	100.00
		ac_range_check_shadow_reg_errors	11.0	406.162576	1	1	100.00
		ac_range_check_shadow_reg_errors_with_csr_rw	84.0	3958.8238220000003	1	1	100.00
		ac_range_check_intr_test	2.0	14.222579	1	1	100.00
		ac_range_check_csr_hw_reset	3.0	200.36839600000002	1	1	100.00
		ac_range_check_csr_rw	2.0	139.446454	1	1	100.00
		ac_range_check_csr_bit_bash	36.0	2533.401411	1	1	100.00
		ac_range_check_csr_aliasing	15.0	693.9066899999999	1	1	100.00
		ac_range_check_same_csr_outstanding	6.0	182.401694	1	1	100.00
		ac_range_check_csr_mem_rw_with_rand_reset	3.0	67.224057	1	1	100.00
		prim_lfsr_gal_test	158.32	0.0	1	1	100.00
		prim_lfsr_fib_test	160.64	0.0	1	1	100.00
		rv_timer_random	0.93	0.0	1	1	100.00
		rv_timer_min	0.75	0.0	0	1	0.00
		rv_timer_max	0.9	0.0	0	1	0.00
		rv_timer_disabled	0.88	0.0	1	1	100.00
		rv_timer_cfg_update_on_fly	34.43	0.0	1	1	100.00
		rv_timer_random_reset	1.33	0.0	0	1	0.00
		rv_timer_stress_all_with_rand_reset	14.41	0.0	1	1	100.00
		rv_timer_stress_all	3.73	0.0	1	1	100.00
		rv_timer_sec_cm	0.89	0.0	1	1	100.00
		rv_timer_alert_test	0.62	0.0	1	1	100.00
		rv_timer_tl_errors	1.19	0.0	1	1	100.00
		rv_timer_tl_intg_err	1.15	0.0	1	1	100.00
		rv_timer_intr_test	0.61	0.0	1	1	100.00
		rv_timer_csr_hw_reset	0.58	0.0	1	1	100.00
		rv_timer_csr_rw	0.62	0.0	1	1	100.00
		rv_timer_csr_bit_bash	2.11	0.0	1	1	100.00
		rv_timer_csr_aliasing	0.71	0.0	1	1	100.00
		rv_timer_same_csr_outstanding	0.84	0.0	1	1	100.00
		rv_timer_csr_mem_rw_with_rand_reset	0.79	0.0	1	1	100.00
		dma_tl_errors	2.0	101.609957	1	1	100.00
		dma_tl_intg_err	2.0	111.508663	1	1	100.00
		dma_intr_test	2.0	49.503536999999994	1	1	100.00
		dma_csr_hw_reset	1.0	65.835243	1	1	100.00
		dma_csr_rw	2.0	35.82519799999999	1	1	100.00
		dma_csr_bit_bash	6.0	534.168664	1	1	100.00
		dma_csr_aliasing	4.0	301.605934	1	1	100.00
		dma_same_csr_outstanding	2.0	133.01970300000002	1	1	100.00
		dma_csr_mem_rw_with_rand_reset	2.0	299.050292	1	1	100.00
		dma_generic_smoke	5.0	774.006357	1	1	100.00
		dma_memory_smoke	5.0	507.941255	1	1	100.00
		dma_handshake_smoke	6.0	344.45976	1	1	100.00
		dma_memory_region_lock	53.0	16963.961327	1	1	100.00
		dma_abort	19.0	1319.651427	1	1	100.00
		dma_short_transfer	128.0	23065.037419	1	1	100.00
		dma_longer_transfer	3.0	123.66622	1	1	100.00
		dma_mem_enabled	18.0	339.78671399999996	1	1	100.00
		dma_config_lock	6.0	361.398977	1	1	100.00
		dma_generic_stress	243.0	19764.674603	1	1	100.00
		dma_memory_stress	757.0	147571.23505199997	1	1	100.00
		dma_handshake_stress	445.0	44731.791659999995	1	1	100.00
		dma_stress_all	28.0	7245.686521	1	1	100.00
		dma_stress_all_with_rand_reset	4.0	432.37787199999997	0	1	0.00
		dma_sec_cm	1.0	18.89325	1	1	100.00
		dma_alert_test	2.0	33.343751	1	1	100.00
		prim_esc_test	0.57	0.0	1	1	100.00
		aes_tl_errors	3.0	448.87231199999997	2	2	100.00
		aes_tl_intg_err	3.0	1083.663613	2	2	100.00
		aes_shadow_reg_errors	3.0	134.317306	2	2	100.00
		aes_shadow_reg_errors_with_csr_rw	3.0	996.3569669999999	2	2	100.00
		aes_csr_hw_reset	2.0	67.970698	2	2	100.00
		aes_csr_rw	2.0	112.544763	2	2	100.00
		aes_csr_bit_bash	8.0	1545.269702	2	2	100.00
		aes_csr_aliasing	3.0	232.060283	2	2	100.00
		aes_same_csr_outstanding	2.0	61.081015	2	2	100.00
		aes_csr_mem_rw_with_rand_reset	2.0	64.888759	2	2	100.00
		rstmgr_tl_errors	2.24	0.0	1	1	100.00
		rstmgr_tl_intg_err	4.55	0.0	1	1	100.00
		rstmgr_csr_hw_reset	1.67	0.0	1	1	100.00
		rstmgr_csr_rw	1.16	0.0	1	1	100.00
		rstmgr_csr_bit_bash	2.48	0.0	1	1	100.00
		rstmgr_csr_aliasing	1.28	0.0	1	1	100.00
		rstmgr_same_csr_outstanding	1.07	0.0	1	1	100.00
		rstmgr_csr_mem_rw_with_rand_reset	1.63	0.0	1	1	100.00
		aes_wake_up	3.0	80.081249	2	2	100.00
		aes_nist_vectors	8.0	306.86845500000004	2	2	100.00
		aes_deinit	4.0	85.507334	2	2	100.00
		aes_man_cfg_err	2.0	79.256495	2	2	100.00
		aes_readability	2.0	53.007879	2	2	100.00
		aes_smoke	3.0	83.232573	2	2	100.00
		aes_config_error	4.0	193.52579	2	2	100.00
		aes_stress	3.0	118.490257	2	2	100.00
		aes_b2b	22.0	382.013816	2	2	100.00
		aes_clear	6.0	461.375652	2	2	100.00
		aes_alert_reset	4.0	287.783588	2	2	100.00
		aes_sideload	4.0	171.568102	2	2	100.00
		aes_reseed	5.0	455.246463	2	2	100.00
		aes_fi	4.0	154.672208	2	2	100.00
		aes_control_fi	1.0	53.864913	2	2	100.00
		aes_cipher_fi	2.0	56.737873	2	2	100.00
		aes_ctr_fi	2.0	71.93636599999999	2	2	100.00
		aes_core_fi	2.0	76.033334	2	2	100.00
		aes_stress_all	39.0	6107.025895	2	2	100.00
		aes_stress_all_with_rand_reset	17.0	7603.0332149999995	0	2	0.00
		aes_sec_cm	5.0	2891.206142	2	2	100.00
		aes_alert_test	2.0	223.096307	2	2	100.00
		rstmgr_smoke	1.23	0.0	1	1	100.00
		rstmgr_por_stretcher	1.22	0.0	1	1	100.00
		rstmgr_reset	5.72	0.0	1	1	100.00
		rstmgr_sw_rst_reset_race	1.15	0.0	1	1	100.00
		rstmgr_sw_rst	1.03	0.0	1	1	100.00
		rstmgr_sec_cm_scan_intersig_mubi	1.13	0.0	1	1	100.00
		rstmgr_leaf_rst_cnsty	3.88	0.0	1	1	100.00
		rstmgr_leaf_rst_shadow_attack	2.12	0.0	1	1	100.00
		rstmgr_stress_all	36.72	0.0	1	1	100.00
		rstmgr_sec_cm	31.84	0.0	1	1	100.00
		rstmgr_alert_test	1.01	0.0	1	1	100.00
		csrng_tl_errors	5.0	84.51483	1	1	100.00
		csrng_tl_intg_err	4.0	184.09199900000002	1	1	100.00
		csrng_intr_test	2.0	28.664788	1	1	100.00
		csrng_csr_hw_reset	2.0	52.630970999999995	1	1	100.00
		csrng_csr_rw	2.0	23.364814	1	1	100.00
		csrng_csr_bit_bash	6.0	233.249514	1	1	100.00
		csrng_csr_aliasing	3.0	28.177143	1	1	100.00
		csrng_same_csr_outstanding	2.0	131.812966	1	1	100.00
		csrng_csr_mem_rw_with_rand_reset	2.0	76.49774099999999	1	1	100.00
		csrng_smoke	6.0	380.828874	1	1	100.00
		csrng_cmds	110.0	5792.424019	1	1	100.00
		csrng_stress_all	1293.0	121840.413868	1	1	100.00
		csrng_intr	5.0	98.765534	1	1	100.00
		csrng_alert	5.0	136.006318	1	1	100.00
		csrng_err	2.0	21.143497	1	1	100.00
		csrng_regwen	2.0	18.665571	1	1	100.00
		csrng_stress_all_with_rand_reset	191.0	9320.655573999999	1	1	100.00
		csrng_sec_cm	6.0	177.516533	1	1	100.00
		csrng_alert_test	3.0	138.2776	1	1	100.00
		rom_ctrl_passthru_mem_tl_intg_err	28.82	0.0	2	2	100.00
		rom_ctrl_tl_errors	11.1	0.0	2	2	100.00
		rom_ctrl_tl_intg_err	53.72	0.0	2	2	100.00
		rom_ctrl_mem_walk	6.87	0.0	2	2	100.00
		rom_ctrl_mem_partial_access	6.19	0.0	2	2	100.00
		rom_ctrl_csr_hw_reset	9.21	0.0	2	2	100.00
		rom_ctrl_csr_rw	6.97	0.0	2	2	100.00
		rom_ctrl_csr_bit_bash	7.48	0.0	2	2	100.00
		rom_ctrl_csr_aliasing	9.75	0.0	2	2	100.00
		rom_ctrl_same_csr_outstanding	7.73	0.0	2	2	100.00
		rom_ctrl_csr_mem_rw_with_rand_reset	8.33	0.0	2	2	100.00
		rom_ctrl_smoke	8.85	0.0	2	2	100.00
		rom_ctrl_stress_all	35.63	0.0	2	2	100.00
		rom_ctrl_max_throughput_chk	8.51	0.0	2	2	100.00
		rom_ctrl_corrupt_sig_fatal_chk	154.36	0.0	2	2	100.00
		rom_ctrl_kmac_err_chk	11.7	0.0	2	2	100.00
		rom_ctrl_stress_all_with_rand_reset	168.63	0.0	2	2	100.00
		rom_ctrl_sec_cm	234.7	0.0	1	2	50.00
		rom_ctrl_alert_test	6.02	0.0	2	2	100.00
		edn_tl_errors	3.55	0.0	1	1	100.00
		edn_tl_intg_err	2.39	0.0	1	1	100.00
		edn_intr_test	0.92	0.0	1	1	100.00
		edn_csr_hw_reset	0.99	0.0	1	1	100.00
		edn_csr_rw	0.9	0.0	1	1	100.00
		edn_csr_bit_bash	4.34	0.0	1	1	100.00
		edn_csr_aliasing	1.31	0.0	1	1	100.00
		edn_same_csr_outstanding	0.95	0.0	1	1	100.00
		edn_csr_mem_rw_with_rand_reset	1.06	0.0	1	1	100.00
		edn_smoke	1.23	0.0	1	1	100.00
		edn_regwen	0.84	0.0	1	1	100.00
		edn_genbits	0.97	0.0	1	1	100.00
		edn_stress_all	4.04	0.0	1	1	100.00
		edn_stress_all_with_rand_reset	59.62	0.0	1	1	100.00
		edn_intr	0.83	0.0	1	1	100.00
		edn_alert	1.11	0.0	1	1	100.00
		edn_err	0.81	0.0	1	1	100.00
		edn_disable	0.83	0.0	1	1	100.00
		edn_disable_auto_req_mode	1.03	0.0	1	1	100.00
		edn_sec_cm	14.48	0.0	1	1	100.00
		edn_alert_test	1.82	0.0	1	1	100.00
		keymgr_dpe_smoke	10.48	0.0	1	1	100.00
		keymgr_dpe_sec_cm	5.76	0.0	1	1	100.00
		keymgr_dpe_alert_test	0.73	0.0	1	1	100.00
		keymgr_dpe_shadow_reg_errors	2.35	0.0	1	1	100.00
		keymgr_dpe_shadow_reg_errors_with_csr_rw	1.85	0.0	1	1	100.00
		keymgr_dpe_tl_errors	2.46	0.0	1	1	100.00
		keymgr_dpe_tl_intg_err	2.03	0.0	1	1	100.00
		keymgr_dpe_intr_test	0.76	0.0	1	1	100.00
		keymgr_dpe_csr_hw_reset	0.99	0.0	1	1	100.00
		keymgr_dpe_csr_rw	1.0	0.0	1	1	100.00
		keymgr_dpe_csr_bit_bash	12.36	0.0	1	1	100.00
		keymgr_dpe_csr_aliasing	2.35	0.0	1	1	100.00
		keymgr_dpe_same_csr_outstanding	1.29	0.0	1	1	100.00
		keymgr_dpe_csr_mem_rw_with_rand_reset	1.4	0.0	1	1	100.00
		alert_handler_shadow_reg_errors_with_csr_rw	894.48	0.0	1	1	100.00
		alert_handler_shadow_reg_errors	78.3	0.0	1	1	100.00
		alert_handler_tl_errors	8.44	0.0	1	1	100.00
		alert_handler_tl_intg_err	1.98	0.0	1	1	100.00
		alert_handler_intr_test	1.42	0.0	1	1	100.00
		alert_handler_csr_hw_reset	3.27	0.0	1	1	100.00
		alert_handler_csr_rw	3.66	0.0	1	1	100.00
		alert_handler_csr_bit_bash	185.45	0.0	1	1	100.00
		alert_handler_csr_aliasing	112.12	0.0	1	1	100.00
		alert_handler_same_csr_outstanding	21.45	0.0	1	1	100.00
		alert_handler_csr_mem_rw_with_rand_reset	9.9	0.0	1	1	100.00
		alert_handler_smoke	48.35	0.0	1	1	100.00
		alert_handler_random_alerts	39.77	0.0	1	1	100.00
		alert_handler_random_classes	15.01	0.0	1	1	100.00
		alert_handler_esc_intr_timeout	14.41	0.0	1	1	100.00
		alert_handler_esc_alert_accum	189.91	0.0	1	1	100.00
		alert_handler_sig_int_fail	38.33	0.0	1	1	100.00
		alert_handler_entropy	304.12	0.0	0	1	0.00
		alert_handler_ping_timeout	14.9	0.0	0	1	0.00
		alert_handler_lpg	1146.95	0.0	1	1	100.00
		alert_handler_lpg_stub_clk	655.7	0.0	1	1	100.00
		alert_handler_entropy_stress	26.23	0.0	1	1	100.00
		alert_handler_stress_all	16.67	0.0	1	1	100.00
		alert_handler_alert_accum_saturation	4.37	0.0	1	1	100.00
		alert_handler_stress_all_with_rand_reset	310.59	0.0	1	1	100.00
		alert_handler_sec_cm	32.19	0.0	1	1	100.00
		lc_ctrl_smoke	1.72	0.0	2	2	100.00
		lc_ctrl_volatile_unlock_smoke	1.14	0.0	2	2	100.00
		lc_ctrl_state_failure	4.94	0.0	0	2	0.00
		lc_ctrl_state_post_trans	4.24	0.0	1	2	50.00
		lc_ctrl_prog_failure	3.09	0.0	2	2	100.00
		lc_ctrl_errors	7.93	0.0	2	2	100.00
		lc_ctrl_security_escalation	7.18	0.0	2	2	100.00
		lc_ctrl_regwen_during_op	9.35	0.0	2	2	100.00
		lc_ctrl_claim_transition_if	0.97	0.0	2	2	100.00
		lc_ctrl_jtag_smoke	6.79	0.0	2	2	100.00
		lc_ctrl_jtag_state_failure	15.17	0.0	0	2	0.00
		lc_ctrl_jtag_state_post_trans	11.83	0.0	2	2	100.00
		lc_ctrl_jtag_prog_failure	4.51	0.0	2	2	100.00
		lc_ctrl_jtag_errors	32.56	0.0	2	2	100.00
		lc_ctrl_jtag_access	8.76	0.0	2	2	100.00
		lc_ctrl_jtag_priority	6.6	0.0	2	2	100.00
		lc_ctrl_jtag_regwen_during_op	26.52	0.0	2	2	100.00
		lc_ctrl_sec_mubi	6.61	0.0	2	2	100.00
		lc_ctrl_sec_token_mux	6.34	0.0	2	2	100.00
		lc_ctrl_sec_token_digest	6.28	0.0	2	2	100.00
		lc_ctrl_stress_all	35.64	0.0	1	2	50.00
		lc_ctrl_stress_all_with_rand_reset	12.93	0.0	0	2	0.00
		lc_ctrl_sec_cm	6.91	0.0	2	2	100.00
		lc_ctrl_alert_test	1.2	0.0	2	2	100.00
		otp_ctrl_tl_errors	4.72	0.0	1	1	100.00
		otp_ctrl_tl_intg_err	19.91	0.0	1	1	100.00
		otp_ctrl_intr_test	1.69	0.0	1	1	100.00
		otp_ctrl_mem_walk	1.5	0.0	1	1	100.00
		otp_ctrl_mem_partial_access	1.56	0.0	1	1	100.00
		otp_ctrl_csr_hw_reset	2.56	0.0	1	1	100.00
		otp_ctrl_csr_rw	2.73	0.0	1	1	100.00
		otp_ctrl_csr_bit_bash	7.18	0.0	1	1	100.00
		otp_ctrl_csr_aliasing	6.02	0.0	1	1	100.00
		otp_ctrl_same_csr_outstanding	2.65	0.0	1	1	100.00
		otp_ctrl_csr_mem_rw_with_rand_reset	1.5	0.0	0	1	0.00
		lc_ctrl_jtag_csr_hw_reset	1.95	0.0	2	2	100.00
		lc_ctrl_jtag_csr_rw	1.33	0.0	2	2	100.00
		lc_ctrl_jtag_csr_bit_bash	9.33	0.0	2	2	100.00
		lc_ctrl_jtag_csr_aliasing	4.98	0.0	2	2	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.55	0.0	2	2	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.92	0.0	2	2	100.00
		lc_ctrl_jtag_alert_test	1.08	0.0	2	2	100.00
		lc_ctrl_tl_errors	2.48	0.0	2	2	100.00
		lc_ctrl_tl_intg_err	2.28	0.0	2	2	100.00
		lc_ctrl_csr_hw_reset	1.32	0.0	2	2	100.00
		lc_ctrl_csr_rw	0.95	0.0	2	2	100.00
		lc_ctrl_csr_bit_bash	1.24	0.0	2	2	100.00
		lc_ctrl_csr_aliasing	1.43	0.0	2	2	100.00
		lc_ctrl_same_csr_outstanding	1.71	0.0	2	2	100.00
		lc_ctrl_csr_mem_rw_with_rand_reset	1.47	0.0	2	2	100.00
		keymgr_shadow_reg_errors	4.79	0.0	1	1	100.00
		keymgr_shadow_reg_errors_with_csr_rw	4.21	0.0	1	1	100.00
		keymgr_tl_errors	2.13	0.0	1	1	100.00
		keymgr_tl_intg_err	2.56	0.0	1	1	100.00
		keymgr_intr_test	0.76	0.0	1	1	100.00
		keymgr_csr_hw_reset	1.05	0.0	1	1	100.00
		keymgr_csr_rw	1.02	0.0	1	1	100.00
		keymgr_csr_bit_bash	8.33	0.0	1	1	100.00
		keymgr_csr_aliasing	3.46	0.0	1	1	100.00
		keymgr_same_csr_outstanding	2.2	0.0	1	1	100.00
		keymgr_csr_mem_rw_with_rand_reset	1.08	0.0	1	1	100.00
		keymgr_smoke	2.39	0.0	1	1	100.00
		keymgr_sideload	1.94	0.0	1	1	100.00
		keymgr_sideload_kmac	1.71	0.0	1	1	100.00
		keymgr_sideload_aes	2.56	0.0	1	1	100.00
		keymgr_sideload_otbn	2.01	0.0	1	1	100.00
		keymgr_random	2.3	0.0	1	1	100.00
		keymgr_cfg_regwen	5.32	0.0	1	1	100.00
		keymgr_direct_to_disabled	2.84	0.0	1	1	100.00
		keymgr_lc_disable	1.64	0.0	1	1	100.00
		keymgr_sw_invalid_input	5.04	0.0	1	1	100.00
		keymgr_hwsw_invalid_input	1.75	0.0	1	1	100.00
		keymgr_kmac_rsp_err	1.71	0.0	1	1	100.00
		keymgr_custom_cm	2.92	0.0	1	1	100.00
		keymgr_sideload_protect	2.14	0.0	1	1	100.00
		keymgr_sync_async_fault_cross	1.27	0.0	1	1	100.00
		keymgr_stress_all	20.9	0.0	1	1	100.00
		keymgr_stress_all_with_rand_reset	4.16	0.0	1	1	100.00
		keymgr_sec_cm	7.91	0.0	1	1	100.00
		keymgr_alert_test	0.81	0.0	1	1	100.00
		otp_ctrl_wake_up	1.81	0.0	1	1	100.00
		otp_ctrl_smoke	8.97	0.0	1	1	100.00
		otp_ctrl_partition_walk	117.6	0.0	0	1	0.00
		otp_ctrl_low_freq_read	59.32	0.0	0	1	0.00
		otp_ctrl_init_fail	3.47	0.0	1	1	100.00
		otp_ctrl_background_chks	8.32	0.0	0	1	0.00
		otp_ctrl_parallel_lc_req	11.03	0.0	1	1	100.00
		otp_ctrl_parallel_lc_esc	2.4	0.0	1	1	100.00
		otp_ctrl_dai_lock	12.53	0.0	1	1	100.00
		otp_ctrl_dai_errs	20.45	0.0	1	1	100.00
		otp_ctrl_check_fail	5.12	0.0	1	1	100.00
		otp_ctrl_macro_errs	36.42	0.0	1	1	100.00
		otp_ctrl_parallel_key_req	15.05	0.0	0	1	0.00
		otp_ctrl_regwen	3.75	0.0	1	1	100.00
		otp_ctrl_test_access	26.58	0.0	0	1	0.00
		otp_ctrl_stress_all_with_rand_reset	2.24	0.0	0	1	0.00
		otp_ctrl_stress_all	3.0	0.0	0	1	0.00
		otp_ctrl_sec_cm	30.87	0.0	0	1	0.00
		otp_ctrl_alert_test	1.89	0.0	1	1	100.00
		entropy_src_tl_errors	3.0	215.471054	1	1	100.00
		entropy_src_tl_intg_err	4.0	65.298098	1	1	100.00
		entropy_src_intr_test	2.0	47.57428	1	1	100.00
		entropy_src_csr_hw_reset	2.0	408.27067700000003	1	1	100.00
		entropy_src_csr_rw	2.0	45.900801	1	1	100.00
		entropy_src_csr_bit_bash	7.0	162.186601	1	1	100.00
		entropy_src_csr_aliasing	7.0	265.882876	1	1	100.00
		entropy_src_same_csr_outstanding	3.0	55.633815999999996	1	1	100.00
		entropy_src_csr_mem_rw_with_rand_reset	2.0	386.72463	1	1	100.00
		entropy_src_smoke	3.0	20.022931	1	1	100.00
		entropy_src_rng	395.0	15042.302818	1	1	100.00
		entropy_src_rng_max_rate	531.0	14016.102891	1	1	100.00
		entropy_src_rng_with_xht_rsps	217.0	8023.752131	1	1	100.00
		entropy_src_stress_all	106.0	20650.198826	1	1	100.00
		entropy_src_fw_ov	111.0	17061.86936	1	1	100.00
		entropy_src_fw_ov_contiguous	38.0	5210.943682	1	1	100.00
		entropy_src_intr	23.0	1128.277497	1	1	100.00
		entropy_src_functional_alerts	6.0	366.132011	1	1	100.00
		entropy_src_cfg_regwen	2.0	29.631473000000003	1	1	100.00
		entropy_src_functional_errors	2.0	114.706565	1	1	100.00
		entropy_src_sec_cm	3.0	106.655851	1	1	100.00
		entropy_src_alert_test	2.0	78.751171	1	1	100.00
		otbn_smoke	10.0	42.76253500000001	0	1	0.00
		otbn_single	6.0	46.618699	0	1	0.00
		otbn_multi	48.0	372.49323100000004	0	1	0.00
		otbn_reset	31.0	92.17106	0	1	0.00
		otbn_multi_err	52.0	146.096953	0	1	0.00
		otbn_imem_err	8.0	27.382357	0	1	0.00
		otbn_dmem_err	6.0	61.245264000000006	0	1	0.00
		otbn_escalate	24.0	173.224353	0	1	0.00
		otbn_alu_bignum_mod_err	7.0	212.36703599999998	0	1	0.00
		otbn_controller_ispr_rdata_err	9.0	24.307475999999998	0	1	0.00
		otbn_mac_bignum_acc_err	11.0	56.407548999999996	0	1	0.00
		otbn_rf_bignum_intg_err	7.0	56.502186	0	1	0.00
		otbn_rf_base_intg_err	7.0	34.456063	0	1	0.00
		otbn_stress_all	11.0	228.59925399999997	0	1	0.00
		otbn_stress_all_with_rand_reset	307.0	6118.256915	0	1	0.00
		otbn_zero_state_err_urnd	8.0	30.67558	0	1	0.00
		otbn_illegal_mem_acc	5.0	13.415938	1	1	100.00
		otbn_sw_errs_fatal_chk	8.0	34.467847	0	1	0.00
		otbn_pc_ctrl_flow_redun	5.0	46.623752	1	1	100.00
		otbn_rnd_sec_cm	36.0	180.189753	0	1	0.00
		otbn_ctrl_redun	5.0	34.016415	0	1	0.00
		otbn_sec_wipe_err	9.0	50.508027999999996	0	1	0.00
		otbn_urnd_err	4.0	9.688411	1	1	100.00
		otbn_sw_no_acc	5.0	52.008655	0	1	0.00
		otbn_mem_gnt_acc_err	5.0	84.296512	1	1	100.00
		otbn_stack_addr_integ_chk	9.0	59.22692	0	1	0.00
		otbn_partial_wipe	8.0	113.101811	1	1	100.00
		otbn_sec_cm	167.0	7198.609438	1	1	100.00
		otbn_alert_test	4.0	39.678892999999995	1	1	100.00
		otbn_passthru_mem_tl_intg_err	21.0	782.0372560000001	1	1	100.00
		otbn_tl_errors	4.0	153.618826	1	1	100.00
		otbn_tl_intg_err	9.0	155.640998	1	1	100.00
		otbn_intr_test	3.0	15.778759	1	1	100.00
		otbn_mem_walk	20.0	368.146134	1	1	100.00
		otbn_mem_partial_access	7.0	192.807024	1	1	100.00
		otbn_csr_hw_reset	3.0	53.208622000000005	1	1	100.00
		otbn_csr_rw	3.0	11.945184999999999	1	1	100.00
		otbn_csr_bit_bash	6.0	93.52674499999999	1	1	100.00
		otbn_csr_aliasing	3.0	45.893626	1	1	100.00
		otbn_same_csr_outstanding	4.0	27.290547999999998	1	1	100.00
		otbn_csr_mem_rw_with_rand_reset	4.0	116.412228	1	1	100.00
		chip_tl_errors	116.67	0.0	0	1	0.00
		chip_prim_tl_access	498.5	0.0	1	1	100.00
		chip_rv_dm_lc_disabled	90.36	0.0	0	1	0.00
		chip_csr_bit_bash	8.53	0.0	0	1	0.00
		chip_csr_aliasing	12.29	0.0	0	1	0.00
		chip_same_csr_outstanding	9.35	0.0	0	1	0.00
		chip_sw_example_rom	30.28	0.0	0	1	0.00
		chip_sw_example_manufacturer	127.836536	0.0	0	1	0.00
		chip_sw_example_concurrency	173.02	0.0	1	1	100.00
		chip_sw_all_escalation_resets	35.46	0.0	0	1	0.00
		chip_sw_rstmgr_rst_cnsty_escalation	884.66	0.0	0	1	0.00
		chip_sw_data_integrity_escalation	111.565006	0.0	0	1	0.00
		chip_sw_sleep_pin_wake	127.888	0.0	0	1	0.00
		chip_sw_sleep_pin_retention	107.506228	0.0	0	1	0.00
		chip_sw_uart_tx_rx	99.694496	0.0	0	1	0.00
		chip_sw_uart_tx_rx_bootstrap	101.741731	0.0	0	1	0.00
		chip_sw_inject_scramble_seed	94.234845	0.0	0	1	0.00
		chip_sw_exit_test_unlocked_bootstrap	80.114164	0.0	0	1	0.00
		chip_sw_uart_rand_baudrate	82.536044	0.0	0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq	72.709895	0.0	0	1	0.00
		chip_sw_i2c_host_tx_rx	93.038727	0.0	0	1	0.00
		chip_sw_i2c_device_tx_rx	80.083794	0.0	0	1	0.00
		chip_sw_spi_device_tpm	51.40465	0.0	0	1	0.00
		chip_sw_spi_host_tx_rx	37.42437	0.0	0	1	0.00
		chip_sw_spi_device_pass_through	2731.07	0.0	1	1	100.00
		chip_sw_spi_device_pass_through_collision	365.65	0.0	0	1	0.00
		chip_sw_gpio	293.49	0.0	1	1	100.00
		chip_sw_kmac_entropy	241.56	0.0	1	1	100.00
		chip_sw_lc_ctrl_otp_hw_cfg	12.044847	0.0	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.004833	0.0	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	10.547755	0.0	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	18.641411	0.0	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	9.77886	0.0	0	1	0.00
		chip_sw_otp_ctrl_vendor_test_csr_access	14.5671	0.0	0	1	0.00
		chip_sw_otp_ctrl_escalation	181.27	0.0	0	1	0.00
		chip_sw_otp_ctrl_nvm_cnt	20.271552	0.0	0	1	0.00
		chip_sw_otp_ctrl_sw_parts	13.74504	0.0	0	1	0.00
		chip_sw_lc_ctrl_transition	10.831525	0.0	0	1	0.00
		chip_sw_lc_ctrl_rma_to_scrap	196.42	0.0	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	174.91	0.0	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	174.11	0.0	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	182.74	0.0	1	1	100.00
		chip_sw_lc_walkthrough_dev	9.535878	0.0	0	1	0.00
		chip_sw_lc_walkthrough_prod	18.573601	0.0	0	1	0.00
		chip_sw_lc_walkthrough_prodend	10.531571	0.0	0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock	470.87	0.0	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	581.68	0.0	1	1	100.00
		chip_sw_lc_walkthrough_rma	13.59795	0.0	0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.820405	0.0	0	1	0.00
		chip_sw_rstmgr_sw_req	283.0	0.0	1	1	100.00
		chip_sw_rstmgr_sw_rst	155.91	0.0	1	1	100.00
		chip_sw_rstmgr_alert_info	306.95	0.0	0	1	0.00
		chip_sw_rstmgr_cpu_info	356.57	0.0	0	1	0.00
		chip_sw_pwrmgr_full_aon_reset	365.39	0.0	1	1	100.00
		chip_sw_pwrmgr_main_power_glitch_reset	11.853915	0.0	0	1	0.00
		chip_sw_pwrmgr_sleep_power_glitch_reset	9.652426	0.0	0	1	0.00
		chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.458235	0.0	0	1	0.00
		chip_sw_pwrmgr_random_sleep_power_glitch_reset	11.209665	0.0	0	1	0.00
		chip_sw_pwrmgr_sleep_disabled	14.22206	0.0	0	1	0.00
		chip_sw_rv_timer_irq	240.38	0.0	1	1	100.00
		chip_sw_soc_proxy_smoketest	138.44	0.0	0	1	0.00
		chip_sw_soc_proxy_external_wakeup	149.11	0.0	0	1	0.00
		chip_sw_soc_proxy_gpios	152.51	0.0	0	1	0.00
		chip_sw_aon_timer_irq	485.88000000000005	0.0	0	1	0.00
		chip_sw_aon_timer_sleep_wdog_sleep_pause	304.35	0.0	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	212.9	0.0	0	1	0.00
		chip_sw_pwrmgr_wdog_reset	11.997445	0.0	0	1	0.00
		chip_sw_aon_timer_wdog_lc_escalate	11.01447	0.0	0	1	0.00
		chip_sw_otbn_randomness	269.55	0.0	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq	2300.65	0.0	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	42.87	0.0	0	1	0.00
		chip_sw_otbn_mem_scramble	359.66	0.0	1	1	100.00
		chip_sw_rv_core_ibex_rnd	233.81	0.0	1	1	100.00
		chip_sw_rv_core_ibex_nmi_irq	361.98	0.0	0	1	0.00
		chip_sw_aes_enc	166.27	0.0	1	1	100.00
		chip_sw_aes_enc_jitter_en	36.72	0.0	0	1	0.00
		chip_sw_aes_idle	163.94	0.0	1	1	100.00
		chip_sw_aes_masking_off	191.59	0.0	1	1	100.00
		chip_sw_alert_test	11.498302	0.0	0	1	0.00
		chip_sw_alert_handler_escalation	10.283099	0.0	0	1	0.00
		chip_sw_alert_handler_ping_timeout	11.487052	0.0	0	1	0.00
		chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.453895	0.0	0	1	0.00
		chip_sw_alert_handler_lpg_sleep_mode_alerts	11.828051	0.0	0	1	0.00
		chip_sw_alert_handler_lpg_sleep_mode_pings	10.168628	0.0	0	1	0.00
		chip_sw_alert_handler_lpg_clkoff	10.60196	0.0	0	1	0.00
		chip_sw_alert_handler_lpg_reset_toggle	10.752899	0.0	0	1	0.00
		chip_sw_alert_handler_entropy	10.443895	0.0	0	1	0.00
		chip_sw_aes_entropy	152.01	0.0	1	1	100.00
		chip_sw_csrng_edn_concurrency	12.206143	0.0	0	1	0.00
		chip_sw_csrng_kat_test	179.79	0.0	1	1	100.00
		chip_sw_csrng_fuse_en_sw_app_read_test	10.726542	0.0	0	1	0.00
		chip_sw_entropy_src_csrng	380.61	0.0	1	1	100.00
		chip_sw_entropy_src_kat_test	165.51	0.0	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	164.77	0.0	1	1	100.00
		chip_sw_hmac_enc	172.03	0.0	1	1	100.00
		chip_sw_hmac_enc_jitter_en	36.84	0.0	0	1	0.00
		chip_sw_hmac_enc_idle	200.7	0.0	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	258.15	0.0	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_prod	269.29	0.0	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	42.51	0.0	0	1	0.00
		chip_sw_kmac_mode_cshake	178.27	0.0	1	1	100.00
		chip_sw_kmac_mode_kmac	223.88	0.0	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	38.4	0.0	0	1	0.00
		chip_sw_kmac_app_rom	31.51	0.0	0	1	0.00
		chip_sw_kmac_idle	152.23	0.0	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	740.48	0.0	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	335.05	0.0	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.131043	0.0	0	1	0.00
		chip_sw_sram_ctrl_execution_main	10.660333	0.0	0	1	0.00
		chip_sw_coremark	9.706436	0.0	0	1	0.00
		chip_plic_all_irqs_0	418.65	0.0	1	1	100.00
		chip_plic_all_irqs_10	338.76	0.0	1	1	100.00
		chip_sw_plic_sw_irq	162.89	0.0	1	1	100.00
		chip_sw_clkmgr_off_aes_trans	179.39	0.0	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	168.28	0.0	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	166.57	0.0	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	165.11	0.0	0	1	0.00
		chip_sw_clkmgr_reset_frequency	11.690634	0.0	0	1	0.00
		chip_sw_clkmgr_jitter	150.09	0.0	1	1	100.00
		chip_sw_clkmgr_sleep_frequency	10.619992	0.0	0	1	0.00
		chip_jtag_csr_rw	103.09	0.0	0	1	0.00
		chip_jtag_mem_access	101.53	0.0	0	1	0.00
		chip_sw_ast_clk_outputs	11.181809	0.0	0	1	0.00
		chip_sw_lc_ctrl_program_error	10.415621	0.0	0	1	0.00
		chip_rv_dm_ndm_reset_req	257.76	0.0	1	1	100.00
		chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.235591	0.0	0	1	0.00
		chip_sw_rv_dm_access_after_wakeup	10.599673	0.0	0	1	0.00
		chip_sw_rv_dm_access_after_escalation_reset	12.154692	0.0	0	1	0.00
		chip_sw_rv_core_ibex_address_translation	188.73	0.0	1	1	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	157.83	0.0	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	160.91	0.0	1	1	100.00
		chip_sw_clkmgr_jitter_reduced_freq	305.2	0.0	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	42.63	0.0	0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	36.48	0.0	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	43.35	0.0	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	36.98	0.0	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	40.58	0.0	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	39.08	0.0	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.997227	0.0	0	1	0.00
		chip_sw_power_virus	10.867634	0.0	0	1	0.00
		chip_sw_dma_inline_hashing	174.98	0.0	1	1	100.00
		chip_sw_dma_abort	165.26	0.0	0	1	0.00
		base_rom_e2e_smoke	10.830534	0.0	0	1	0.00
		rom_e2e_smoke	12.061064	0.0	0	1	0.00
		rom_e2e_shutdown_exception_c	10.390471	0.0	0	1	0.00
		rom_e2e_shutdown_output	10.774072	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.414876	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.138779	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.921434	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	9.731646	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	9.371294	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	9.314065	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.010275	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.114755	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.30417	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.163294	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	65.517505	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	65.010449	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	68.261766	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	67.397287	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	53.6222	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	65.932702	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	54.620686	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	35.498897	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	62.74369600000001	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	58.828744	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	44.712036	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	55.749974	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	45.373387	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	38.509382	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	38.710843	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	9.722533	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.211057	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.991487	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	9.59212	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	14.582397	0.0	0	1	0.00
		rom_e2e_asm_init_test_unlocked0	12.29639	0.0	0	1	0.00
		rom_e2e_asm_init_dev	10.071974	0.0	0	1	0.00
		rom_e2e_asm_init_prod	14.736026	0.0	0	1	0.00
		rom_e2e_asm_init_prod_end	14.661948	0.0	0	1	0.00
		rom_e2e_asm_init_rma	9.514635	0.0	0	1	0.00
		rom_e2e_jtag_debug_test_unlocked0	12.041568	0.0	0	1	0.00
		rom_e2e_jtag_debug_dev	10.075991	0.0	0	1	0.00
		rom_e2e_jtag_debug_rma	12.341506	0.0	0	1	0.00
		rom_e2e_jtag_inject_test_unlocked0	9.933924	0.0	0	1	0.00
		rom_e2e_jtag_inject_dev	9.540038	0.0	0	1	0.00
		rom_e2e_jtag_inject_rma	9.517485	0.0	0	1	0.00
		rom_e2e_static_critical	9.968578	0.0	0	1	0.00
		rom_e2e_keymgr_init_rom_ext_meas	9.783562	0.0	0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	9.489153	0.0	0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.030995	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	9.18023	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	9.361266	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	9.928698	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	9.636914	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	9.772704	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	9.694917	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.233528	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	9.737058	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	9.64442	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	9.871133	0.0	0	1	0.00
		rom_volatile_raw_unlock	10.468399	0.0	0	1	0.00
		rom_raw_unlock	9.328454	0.0	0	1	0.00
		rom_e2e_self_hash	9.684973	0.0	0	1	0.00
		chip_sw_uart_smoketest_signed	9.609872	0.0	0	1	0.00
		rom_keymgr_functest	9.6762	0.0	0	1	0.00
		chip_sw_aes_smoketest	143.89	0.0	1	1	100.00
		chip_sw_aon_timer_smoketest	142.77	0.0	1	1	100.00
		chip_sw_clkmgr_smoketest	127.55000000000001	0.0	1	1	100.00
		chip_sw_csrng_smoketest	134.39	0.0	1	1	100.00
		chip_sw_entropy_src_smoketest	176.6	0.0	1	1	100.00
		chip_sw_gpio_smoketest	142.33	0.0	1	1	100.00
		chip_sw_hmac_smoketest	165.56	0.0	1	1	100.00
		chip_sw_kmac_smoketest	154.67	0.0	1	1	100.00
		chip_sw_mbx_smoketest	277.0	0.0	1	1	100.00
		chip_sw_otbn_smoketest	168.15	0.0	1	1	100.00
		chip_sw_otp_ctrl_smoketest	133.85	0.0	1	1	100.00
		chip_sw_rv_plic_smoketest	129.13	0.0	1	1	100.00
		chip_sw_rv_timer_smoketest	193.7	0.0	1	1	100.00
		chip_sw_rstmgr_smoketest	128.6	0.0	1	1	100.00
		chip_sw_sram_ctrl_smoketest	129.39	0.0	1	1	100.00
		chip_sw_uart_smoketest	135.08	0.0	1	1	100.00
		chip_padctrl_attributes	2.68	0.0	0	1	0.00
		TOTAL			991	1241	79.85

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
93.61	96.82	92.25	96.79	90.86	86.04	--	97.01	84.96

Failure Buckets

• Job returned non-zero exit code has 122 failures:

  • Test chip_sw_example_manufacturer has 1 failures.

    • 0.chip_sw_example_manufacturer.95692376931862576282942068763541771465730963135385480623615198307650456417835
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

        Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 118.966s, Critical Path: 0.03s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test chip_sw_data_integrity_escalation has 1 failures.

    • 0.chip_sw_data_integrity_escalation.71140330200888583099782412626702884805243896035691086620351164368706829053819
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

        Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 102.749s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test chip_sw_sleep_pin_wake has 1 failures.

    • 0.chip_sw_sleep_pin_wake.99844516830924498823982878970268293796949280414822999475399597211264580267647
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 119.225s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test chip_sw_sleep_pin_retention has 1 failures.

    • 0.chip_sw_sleep_pin_retention.48348263766403579191792298636957732703259018465225139790624319769990246070029
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 98.716s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test chip_sw_uart_tx_rx has 1 failures.

    • 0.chip_sw_uart_tx_rx.110846664066325187421435912809816183752901195899604040072924944177348608682742
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

        Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 91.212s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • ... and 117 more tests.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 11 failures:

  • Test chip_sw_otbn_ecdsa_op_irq_jitter_en has 1 failures.

    • 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.99898021418935604894580468873352121431261329500775276302181959374628358532914
      Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log

        UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_aes_enc_jitter_en has 1 failures.

    • 0.chip_sw_aes_enc_jitter_en.20603025714156984262618206384969464315066363062166200183895447573275012320942
      Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_hmac_enc_jitter_en has 1 failures.

    • 0.chip_sw_hmac_enc_jitter_en.91323951635047544164781513237202936613145788214490917846803016828098103067685
      Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.51359539670151336938387766613998476615104424914610575419217990021283141249673
      Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log

        UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.

    • 0.chip_sw_kmac_mode_kmac_jitter_en.107751786586816366241523179768677572546269051878337514572842011014993698186858
      Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log

        UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 6 more tests.

• Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 9 failures:

  • Test lc_ctrl_state_failure has 2 failures.

    • 0.lc_ctrl_state_failure.53154981232751888833260626566858476807148487411914378579185061142839458440199
      Line 430, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_state_failure/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @  21844338 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @  21844338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.lc_ctrl_state_failure.87613434904860649494191159705166402353387882990071561210195230534820494568114
      Line 208, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_state_failure/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @  20421936 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @  20421936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_state_post_trans has 1 failures.

    • 0.lc_ctrl_state_post_trans.14590821500246795531730925776132773471892369934130166203601779375818782903788
      Line 205, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_state_post_trans/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @  68049409 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @  68049409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_jtag_state_failure has 2 failures.

    • 0.lc_ctrl_jtag_state_failure.72953098820918615269812650773154806597910561829143876719873020049335725561126
      Line 1589, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 2708492212 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 2708492212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.lc_ctrl_jtag_state_failure.59557880929466649483374343475575846628984374245833996980474157042748420374752
      Line 653, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 217779284 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 217779284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 0.lc_ctrl_stress_all.65310751592023785510283807073162708900736320089660760650949709342192070705938
      Line 577, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 988850041 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 988850041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.33250323122681021214590590675048777155883600606692086576950574088887842302309
      Line 1369, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 399648298 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 399648298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.lc_ctrl_stress_all_with_rand_reset.65536422759134025112567347004036668957672229288010335116196116161367943616275
      Line 1122, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 5328284794 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 5328284794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 1 more tests.

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@*_*.mnemonic_cp) is an illegal value. has 9 failures:

  • Test otbn_multi has 1 failures.

    • 0.otbn_multi.50376943057587521582896647050688859584890499275414803621977535691702357825521
      Line 149, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 11623925 PS + 23) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 11644758 PS + 22) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 11644758 PS + 22) Sampled value (7566690) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 11644758 PS + 22) Sampled value (7566690) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1363):(Time: 11644758 PS + 22) Sampled value (7566690) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_addsub_cg@4225_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_escalate has 1 failures.

    • 0.otbn_escalate.88806477890211569080164758336540521871784534368703850528655227618382682333086
      Line 112, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 22940450 PS + 24) Sampled value (2020569705) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1462):(Time: 22940450 PS + 24) Sampled value (2020569705) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_log_binop_cg@4233_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 22960858 PS + 21) Sampled value (2020569705) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 22960858 PS + 21) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 22960858 PS + 21) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_alu_bignum_mod_err has 1 failures.

    • 0.otbn_alu_bignum_mod_err.46800910254515824593411657542926397242706040368147122082779149760404097045401
      Line 107, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 17153157 PS + 21) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 17194824 PS + 21) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 17194824 PS + 21) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1223):(Time: 17194824 PS + 21) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@4217_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 17236491 PS + 22) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

  • Test otbn_mac_bignum_acc_err has 1 failures.

    • 0.otbn_mac_bignum_acc_err.49379595272097593401020208351752988169660598730190376817238449546570014531403
      Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 7366587 PS + 20) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 7387420 PS + 22) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 7387420 PS + 22) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 7387420 PS + 22) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 7408253 PS + 23) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

  • Test otbn_rf_base_intg_err has 1 failures.

    • 0.otbn_rf_base_intg_err.68942044246363825292480104091873985367261661838698061873253470338740342873279
      Line 111, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 9849746 PS + 23) Sampled value (427138642547) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 9870154 PS + 20) Sampled value (427138642547) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 9870154 PS + 20) Sampled value (7892850) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 9870154 PS + 20) Sampled value (7892850) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 9890562 PS + 20) Sampled value (7892850) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

  • ... and 4 more tests.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:

  • Test rv_dm_sba_tl_access has 1 failures.

    • 0.rv_dm_sba_tl_access.56646743605382451474209699760562440198084204837660272296860469749398431620499
      Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_delayed_resp_sba_tl_access has 1 failures.

    • 0.rv_dm_delayed_resp_sba_tl_access.97059314157486690440377982128554226238529633063043112785916557797133126048527
      Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_bad_sba_tl_access has 1 failures.

    • 0.rv_dm_bad_sba_tl_access.70759362100075415397385842467067447632709992079645275582461364001929080547171
      Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_autoincr_sba_tl_access has 1 failures.

    • 0.rv_dm_autoincr_sba_tl_access.47650192652623270922896440476853521817900525453618613378488008562494637320448
      Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_scanmode has 1 failures.

    • 0.rv_dm_scanmode.96398468892401633001743474939262567377992300786421301271858240137920818088247
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_scanmode/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 5 failures:

  • Test chip_sw_rstmgr_cpu_info has 1 failures.

    • 0.chip_sw_rstmgr_cpu_info.63375992209383910541421495245364929438202800642152032764098023265869435202141
      Line 436, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 375.200000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 375.200000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_clkmgr_off_aes_trans has 1 failures.

    • 0.chip_sw_clkmgr_off_aes_trans.56928211267309779414601507771737070090947274000145722456393481478247576221726
      Line 418, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.680000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.680000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

    • 0.chip_sw_clkmgr_off_hmac_trans.14039456114032382339887787059626665416951911243690042252782228471308655612877
      Line 411, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

    • 0.chip_sw_clkmgr_off_kmac_trans.110225753369649332891139193717319645085880217156270564267985017456653518438969
      Line 412, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.632000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.632000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

    • 0.chip_sw_clkmgr_off_otbn_trans.53852304002457356795626365107549606908530344784155393074616404780506723043700
      Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.696000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.696000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@*_*.mnemonic_cp) is an illegal value. has 4 failures:

  • Test otbn_imem_err has 1 failures.

    • 0.otbn_imem_err.34166604702905347744991736005728407547988773534235362782389116427856564585769
      Line 115, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_imem_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 8820595 PS + 21) Sampled value (6385252) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1462):(Time: 8820595 PS + 21) Sampled value (6385252) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_log_binop_cg@4233_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 8830696 PS + 23) Sampled value (6385252) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 8830696 PS + 23) Sampled value (7107945) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1332):(Time: 8830696 PS + 23) Sampled value (7107945) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_u_cg@4224_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_dmem_err has 1 failures.

    • 0.otbn_dmem_err.41300695021524653055459781911538177045983441252378889796630232770588488754689
      Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 20967204 PS + 22) Sampled value (28530) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1462):(Time: 20967204 PS + 22) Sampled value (28530) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_log_binop_cg@4233_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 21022760 PS + 19) Sampled value (28530) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 21022760 PS + 19) Sampled value (6971756) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1240):(Time: 21022760 PS + 19) Sampled value (6971756) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_j_cg@4218_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_stress_all has 1 failures.

    • 0.otbn_stress_all.7754618034887572644636260563057108888905592756422165469474938756961665797066
      Line 142, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 26984066 PS + 20) Sampled value (28530) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4222_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1462):(Time: 26984066 PS + 20) Sampled value (28530) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_log_binop_cg@4234_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 27060989 PS + 23) Sampled value (28530) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 27060989 PS + 23) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 27060989 PS + 23) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4217_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.27561353886432530817891410143179261381240459787158517896629726146748982677609
      Line 145, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 47916686 PS + 20) Sampled value (6382692) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4224_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1363):(Time: 47916686 PS + 20) Sampled value (6382692) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_addsub_cg@4228_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 47958353 PS + 21) Sampled value (6382692) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4202_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 47958353 PS + 21) Sampled value (1936875881) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4202_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1223):(Time: 47958353 PS + 21) Sampled value (1936875881) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@4220_1.mnemonic_cp) is an illegal value.
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:

  • Test chip_csr_bit_bash has 1 failures.

    • 0.chip_csr_bit_bash.111279789589681966316161698096756989675027582101741575401727914760830339312671
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_csr_aliasing has 1 failures.

    • 0.chip_csr_aliasing.18666941557803646761566706153225156833310593380511051018366713857920086241131
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_same_csr_outstanding has 1 failures.

    • 0.chip_same_csr_outstanding.55651545141609421499144231089225859106149928303087225104647841277719682449721
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.90944798923213504869350124055846366226090539928342493555600208101224078785784
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  56613989 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  56613989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.114280810328151869875488705951528800668518645949426217640319093658844886641049
      Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10697748724 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 10697748724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 2 failures:

  • Test rv_dm_jtag_dmi_debug_disabled has 1 failures.

    • 0.rv_dm_jtag_dmi_debug_disabled.68231717530091247771008953773096129667384403599673961690741296734314656688912
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log

        UVM_ERROR @ 684871964 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2199273549 [0x8316404d] vs 0 [0x0])
        UVM_INFO @ 684871964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_stress_all has 1 failures.

    • 0.rv_dm_stress_all.14728549123041314345501478673617832063089635648299688634785980239535050292509
      Line 80, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log

        UVM_ERROR @ 7386340817 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (32064426 [0x1e943aa] vs 0 [0x0])
        UVM_INFO @ 7386340817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 2 failures:

  • Test clkmgr_frequency has 1 failures.

    • 0.clkmgr_frequency.9717909166791859516414696721568274001640889358275658707722454192771872437198
      Line 72, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log

        UVM_ERROR @  13023967 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00
        UVM_INFO @  13023967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 0.clkmgr_stress_all_with_rand_reset.92553493962763113570604587461563955413241611720262220174692646153506999452639
      Line 75, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  32645842 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00
        UVM_INFO @  32645842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* has 2 failures:

  • Test clkmgr_frequency_timeout has 1 failures.

    • 0.clkmgr_frequency_timeout.109750167557039752425432199009933255449618629595667276069414180067067625601817
      Line 75, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log

        UVM_ERROR @   7878643 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
        UVM_INFO @   7878643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test clkmgr_stress_all has 1 failures.

    • 0.clkmgr_stress_all.98068675155641370573215258920790337639284391128209319728570875189917798353784
      Line 82, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all/latest/run.log

        UVM_ERROR @ 126844503 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
        UVM_INFO @ 126844503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * has 2 failures:

  • Test clkmgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.clkmgr_shadow_reg_errors_with_csr_rw.105756169730971886165571042050463433331892741711291455688698841321241658178212
      Line 72, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @   2638446 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
        UVM_INFO @   2638446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test clkmgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.clkmgr_csr_mem_rw_with_rand_reset.94297749110660642544095315465785082718532662758905098163228396481302913665859
      Line 73, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  13601391 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
        UVM_INFO @  13601391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 0.sram_ctrl_sec_cm.49531692668859200833672980562812555331513049956299142938292475347164948812637
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6354213 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6354213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.sram_ctrl_sec_cm.68666783345401196517032122115810891677159413639208785165749342912612454015688
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  93034021 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  93034021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.31452090730786140899927938278619180606039502925460455776498672896065063837480
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @  74088294 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf1fcbd04) == 0x1
        UVM_INFO @  74088294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.109816022996265469038846939720782750918808595641778171947981088883741468272977
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 400663132 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x4484cb04) == 0x1
        UVM_INFO @ 400663132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * has 2 failures:

  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.otp_ctrl_csr_mem_rw_with_rand_reset.30434679906239753255857531322641897236466158506162709247677880486070281210766
      Line 88, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  32954931 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
        UVM_INFO @  32954931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.97329362761206707125971739500919395417669388287186033059499420458332234565245
      Line 88, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  47031969 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
        UVM_INFO @  47031969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_loopi_cg@*_*.mnemonic_cp) is an illegal value. has 2 failures:

  • Test otbn_multi_err has 1 failures.

    • 0.otbn_multi_err.54340226819916761741339217257355797548657055990101004504712013286915829228483
      Line 201, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1270):(Time: 4167797 PS + 24) Sampled value (465726042217) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_loopi_cg@4220_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 4177898 PS + 23) Sampled value (465726042217) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 4177898 PS + 23) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 4177898 PS + 23) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 4187999 PS + 23) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

  • Test otbn_rnd_sec_cm has 1 failures.

    • 0.otbn_rnd_sec_cm.93831529919263029983897035502104154938613692414314350376245641709178874441801
      Line 105, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rnd_sec_cm/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1270):(Time: 25591216 PS + 28) Sampled value (465726042217) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_loopi_cg@4220_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 25612050 PS + 20) Sampled value (465726042217) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 25612050 PS + 20) Sampled value (27767) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 25612050 PS + 20) Sampled value (27767) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1488):(Time: 25612050 PS + 20) Sampled value (27767) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_xw_cg@4234_1.mnemonic_cp) is an illegal value.
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_wcsr_cg@*_*.mnemonic_cp) is an illegal value. has 2 failures:

  • Test otbn_rf_bignum_intg_err has 1 failures.

    • 0.otbn_rf_bignum_intg_err.51131857152470701263301000255303959309632654591429502743974253365447490977037
      Line 105, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_bignum_intg_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1344):(Time: 4354844 PS + 25) Sampled value (27705693569249906) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_wcsr_cg@4223_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 4365261 PS + 27) Sampled value (27705693569249906) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 4365261 PS + 27) Sampled value (108225364848502) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1039):(Time: 4365261 PS + 27) Sampled value (108225364848502) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_bnmov_cg@4209_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 4375678 PS + 21) Sampled value (108225364848502) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

  • Test otbn_zero_state_err_urnd has 1 failures.

    • 0.otbn_zero_state_err_urnd.74156443307112729182255604326077419684918482558743258477548536577856623357573
      Line 103, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1344):(Time: 12237363 PS + 30) Sampled value (27705693569249906) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_wcsr_cg@4223_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 12254030 PS + 23) Sampled value (27705693569249906) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 12254030 PS + 23) Sampled value (108225365243234) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 790):(Time: 12254030 PS + 23) Sampled value (108225365243234) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_bnaf_cg@4201_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 12270697 PS + 21) Sampled value (108225365243234) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

• UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

  • Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation.46581705256813245162057300683575815208086998694868956473008754461207316666835
      Line 431, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

        UVM_ERROR @ 268.307000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (12750468076520030285235498272389166615604210749242973944801740513530637510550535005058470832176956428570591784087438974283402425624371469278141678562401372 [0xf372fd5eaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd375244daf7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 268.307000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation_prod.58873245020456572479665283449670649388982593911591966446179404061591599929410
      Line 419, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

        UVM_ERROR @ 268.131000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11426215826386761871207637834117486890367575319800169440812494288196980080792360360361498387773194355992506443477716850009418373000650040061914820431404124 [0xda2a2df7aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35c7c9d067f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 268.131000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42094) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

  • Test chip_jtag_csr_rw has 1 failures.

    • 0.chip_jtag_csr_rw.45991844916344447119151974474492406824668614118340025092485373191262145209223
      Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

        UVM_ERROR @ 117.025000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42094) { a_addr: 'h30480000  a_data: 'hdb7c100  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h1  a_user: 'h248a5  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 117.025000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_jtag_mem_access has 1 failures.

    • 0.chip_jtag_mem_access.27410662380134881898095211766422726553707537564480317761064534795226008770500
      Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

        UVM_ERROR @ 117.004000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42094) { a_addr: 'h30480000  a_data: 'ha13f1429  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1d  a_opcode: 'h1  a_user: 'h24881  d_param: 'h0  d_source: 'h1d  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 117.004000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.71793629919897139937629622634569919738417544836839221089641783092830207385363
      Line 122, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 13330088257 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @1970213
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.101087293428942445752505895682591136085724355878464620634678269729073184791479
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 901115584 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 901115584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.67207665973659031414321122791338585349642351482466939598578250035575850180544
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

            Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
        UVM_ERROR @ 1901832442 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
        UVM_INFO @ 1901832442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.5919027760529852904003227662227217619317583440164513951889806394734296024957
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10137772438 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10137772438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.20270892128915015443336901693994892177268311281740526001540528925297032005884
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 461921077 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 461921077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6652) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test rv_dm_tap_fsm_rand_reset has 1 failures.

    • 0.rv_dm_tap_fsm_rand_reset.43560490486115186608826803721571618304034932081912723649506783800815097152370
      Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log

        UVM_ERROR @  32241143 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6652) { a_addr: 'h9a0c86d4  a_data: 'hed085837  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6e  a_opcode: 'h4  a_user: 'h1869b  d_param: 'h0  d_source: 'h6e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @  32241143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5808) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test rv_dm_tl_errors has 1 failures.

    • 0.rv_dm_tl_errors.47055913763616236865466178524204846841621452569645160552284288741303099390534
      Line 75, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log

        UVM_ERROR @  51566301 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5808) { a_addr: 'h3e9234d0  a_data: 'h789dcee2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8f  a_opcode: 'h4  a_user: 'h18562  d_param: 'h0  d_source: 'h8f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @  51566301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5566) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test rv_dm_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.rv_dm_csr_mem_rw_with_rand_reset.91078211780684970091976661828524833722130552781387459043291945213998599669388
      Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  99786260 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5566) { a_addr: 'hddb89474  a_data: 'ha50cd573  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hcd  a_opcode: 'h4  a_user: 'h18b07  d_param: 'h0  d_source: 'hcd  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @  99786260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs * [])` has 1 failures:

  • Test rv_dm_mem_tl_access_resuming has 1 failures.

    • 0.rv_dm_mem_tl_access_resuming.54851923220026386606511818124207158355101879152934068367588431576117675837021
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log

        UVM_ERROR @ 543452704 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 543452704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 1 failures:

  • Test rv_dm_hart_unavail has 1 failures.

    • 0.rv_dm_hart_unavail.76357899208359729774427368686697777542405832558998112658721512554953520718280
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest/run.log

        UVM_ERROR @  64580714 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
        UVM_INFO @  64580714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6492) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test rv_dm_stress_all_with_rand_reset has 1 failures.

    • 0.rv_dm_stress_all_with_rand_reset.74029311414856437447493726489584027711267977617993098046509614128304986986801
      Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  36545700 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6492) { a_addr: 'h52e9b614  a_data: 'hb476638b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h7c  a_opcode: 'h4  a_user: 'h1a7bf  d_param: 'h0  d_source: 'h7c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @  36545700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:

  • Test gpio_stress_all_with_rand_reset has 1 failures.

    • 0.gpio_stress_all_with_rand_reset.112149986258082361569949948460732926464791224984446703110339007847449237488805
      Line 216, in log /nightly/current_run/scratch/master/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 769986246 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
        UVM_INFO @ 769986246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:642) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:

  • Test gpio_same_csr_outstanding has 1 failures.

    • 0.gpio_same_csr_outstanding.100819598036993312068309314648783331629533772934500374651093067935178577217278
      Line 74, in log /nightly/current_run/scratch/master/gpio-sim-vcs/0.gpio_same_csr_outstanding/latest/run.log

        UVM_ERROR @  41478858 ps: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xcdb7eb7c read out mismatch
        UVM_INFO @  41478858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.44211684562725711276425164476731144148688708489662761394364237092600926964861
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4643727 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[84])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4643727 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4643727 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[980])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.109533369645985800987130306146029083937581376095132519290747793013211917487240
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1073481 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb1fe0a [101100011111111000001010] vs 0x0 [0])
        UVM_ERROR @   1106481 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb2042e [101100100000010000101110] vs 0x0 [0])
        UVM_ERROR @   1155481 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x869b4c [100001101001101101001100] vs 0x0 [0])
        UVM_ERROR @   1251481 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbcb547 [101111001011010101000111] vs 0x0 [0])
        UVM_ERROR @   1259481 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfb9a65 [111110111001101001100101] vs 0x0 [0])
      

• UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en has 1 failures:

  • Test clkmgr_regwen has 1 failures.

    • 0.clkmgr_regwen.56218233995617696801218169490812733192063630864441021736187905722902555973411
      Line 71, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_regwen/latest/run.log

        UVM_ERROR @   5595322 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 7 [0x7]) reg name: clkmgr_reg_block.io_meas_ctrl_en
        UVM_INFO @   5595322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * has 1 failures:

  • Test clkmgr_tl_intg_err has 1 failures.

    • 0.clkmgr_tl_intg_err.51009043070416722919660914231065171799509998088681093237066759113191998627521
      Line 79, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest/run.log

        UVM_ERROR @  24709482 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
        UVM_INFO @  24709482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * has 1 failures:

  • Test clkmgr_csr_bit_bash has 1 failures.

    • 0.clkmgr_csr_bit_bash.114236047686258354134138726373492678226251449118591861253749403018800169180301
      Line 72, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest/run.log

        UVM_ERROR @ 185867364 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0
        UVM_INFO @ 185867364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:642) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:

  • Test clkmgr_same_csr_outstanding has 1 failures.

    • 0.clkmgr_same_csr_outstanding.38484963009705985605105626117768883523876394552851267484454114041193771002779
      Line 72, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest/run.log

        UVM_ERROR @  12777221 ps: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (87421 [0x1557d] vs 60554 [0xec8a]) addr 0xf359ef74 read out mismatch
        UVM_INFO @  12777221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.11519445749637868824081602021372845540223813778240612452407826200100584636249
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 218066291 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x13) != exp (0x45)
        UVM_INFO @ 218066291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.111851490204459928357955875327110676462660764331782902840694363773607296378104
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 534304127 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_ERROR @ 534304127 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
        UVM_ERROR @ 656013434 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_ERROR @ 656013434 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
        UVM_ERROR @ 1023141371 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
      

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed has 1 failures:

  • Test mbx_stress_zero_delays has 1 failures.

    • 0.mbx_stress_zero_delays.79589770289721094655064698911832167159233778146824899835142634806080907377167
      Line 95, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,287): (time 40328364 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
        UVM_ERROR @  40328364 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
        UVM_INFO @  40328364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (ac_range_check_scoreboard.sv:362) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state has 1 failures:

  • Test ac_range_check_stress_all has 1 failures.

    • 0.ac_range_check_stress_all.9166258235390554829691014021152312054673562117801153162076782349821363470335
      Line 26865, in log /nightly/current_run/scratch/master/ac_range_check-sim-xcelium/0.ac_range_check_stress_all/latest/run.log

        UVM_ERROR @ 2670079578 ps: (ac_range_check_scoreboard.sv:362) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
        UVM_INFO @ 2670079578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.41859957035149532201248317505384667386009950352604515404906435212176414932597
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 175438538 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 175438538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.33444133377557836762942640128707066001776191103631822833845596617079880398821
      Line 91, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  432377872ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  432377872ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.115118610540079278428424535239446499731512781104505383014349698084052200844518
      Line 399, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 110449050 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 110449050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.41183446043468057805750037437110744205193100694587680377699347375825535676280
      Line 624, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7603033215 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 7603033215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.97449219839392591234562501776206674342760743878084809092558499717837145018389
      Line 116, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 19781166ps failed at 19781166ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 19781166ps failed at 19781166ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

• UVM_ERROR (alert_handler_scoreboard.sv:487) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_accum_cnt has 1 failures:

  • Test alert_handler_entropy has 1 failures.

    • 0.alert_handler_entropy.42136036335442269645177975278413890090897695512666361332522894863951677455727
      Line 77, in log /nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_entropy/latest/run.log

        UVM_ERROR @ 37198185627 ps: (alert_handler_scoreboard.sv:487) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (343 [0x157] vs 342 [0x156]) reg name: alert_handler_reg_block.classa_accum_cnt
        UVM_INFO @ 37198185627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == gmv(ral.loc_alert_cause[i]) (* [] vs * [])` has 1 failures:

  • Test alert_handler_ping_timeout has 1 failures.

    • 0.alert_handler_ping_timeout.35416717191918315181957722682989995576140185237762636913110008113764709550627
      Line 77, in log /nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 1866457726 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 1866457726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * has 1 failures:

  • Test otp_ctrl_partition_walk has 1 failures.

    • 0.otp_ctrl_partition_walk.98358335026632139993058069364160240466794524392563179989987908256627399627853
      Line 165390, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest/run.log

        UVM_ERROR @ 5918972116 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
        UVM_INFO @ 5918972116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_low_freq_read has 1 failures.

    • 0.otp_ctrl_low_freq_read.107586721980938868021687845596112642860229336345898350124558956808737418121389
      Line 86, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest/run.log

        UVM_ERROR @ 21880200392 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
        UVM_INFO @ 21880200392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:649) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr has 1 failures:

  • Test otp_ctrl_background_chks has 1 failures.

    • 0.otp_ctrl_background_chks.29807288568370993477736970453564888012137416550152604619312098750254249909470
      Line 7114, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest/run.log

        UVM_ERROR @ 1863444472 ps: (otp_ctrl_scoreboard.sv:649) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
        UVM_INFO @ 1863444472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:936) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * has 1 failures:

  • Test otp_ctrl_parallel_key_req has 1 failures.

    • 0.otp_ctrl_parallel_key_req.252530661676628793632467003465309484646789406135746045994740196569926348422
      Line 17373, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest/run.log

        UVM_ERROR @ 1529325989 ps: (otp_ctrl_scoreboard.sv:936) [uvm_test_top.env.scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (541073472 [0x20402040] vs 536879168 [0x20002040]) reg name: status, compare_mask 0
        UVM_INFO @ 1529325989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 1 failures:

  • Test otp_ctrl_test_access has 1 failures.

    • 0.otp_ctrl_test_access.106717348512459657776948357909208140035223617277402577193270259588105208325008
      Line 13930, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest/run.log

        UVM_ERROR @ 6977766047 ps: (otp_ctrl_scoreboard.sv:1250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 6977766047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* has 1 failures:

  • Test otp_ctrl_stress_all has 1 failures.

    • 0.otp_ctrl_stress_all.98299766612060757566390765725608733256015604437945658100827878097074832775863
      Line 672, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 130624323 ps: (otp_ctrl_scoreboard.sv:1250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
        UVM_INFO @ 130624323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire has 1 failures:

  • Test otp_ctrl_sec_cm has 1 failures.

    • 0.otp_ctrl_sec_cm.96500955670180317296934377625953051130131645841908174111599131950409152882294
      Line 354, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest/run.log

        UVM_ERROR @ 24664631515 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
        UVM_INFO @ 24664631515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_u_cg@*_*.mnemonic_cp) is an illegal value. has 1 failures:

  • Test otbn_smoke has 1 failures.

    • 0.otbn_smoke.101721823371830797863286800661885406835618568298816185096710946367419710066547
      Line 114, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1332):(Time: 28415687 PS + 23) Sampled value (7107945) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_u_cg@4224_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 28425891 PS + 21) Sampled value (7107945) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 28425891 PS + 21) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 28425891 PS + 21) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 28436095 PS + 23) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@*_*.mnemonic_cp) is an illegal value. has 1 failures:

  • Test otbn_single has 1 failures.

    • 0.otbn_single.103842143826743736839696170429538224704176831116036350304785258957121573005786
      Line 118, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_single/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1223):(Time: 13493474 PS + 23) Sampled value (1936485481) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@4217_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 13535141 PS + 26) Sampled value (1936485481) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 13535141 PS + 26) Sampled value (7565921) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 13535141 PS + 26) Sampled value (7565921) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 13576808 PS + 25) Sampled value (7565921) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_s_cg@*_*.mnemonic_cp) is an illegal value. has 1 failures:

  • Test otbn_reset has 1 failures.

    • 0.otbn_reset.17238587165264722864607410250246986842709597055851919555927283010538896313752
      Line 117, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_reset/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1314):(Time: 4272574 PS + 23) Sampled value (29559) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_s_cg@4222_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1488):(Time: 4272574 PS + 23) Sampled value (29559) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_xw_cg@4234_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 4282991 PS + 24) Sampled value (29559) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 4282991 PS + 24) Sampled value (6385252) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 4282991 PS + 24) Sampled value (6385252) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_j_cg@*_*.mnemonic_cp) is an illegal value. has 1 failures:

  • Test otbn_controller_ispr_rdata_err has 1 failures.

    • 0.otbn_controller_ispr_rdata_err.107891939566702735975356177142828700381545124445394178476779888996299524370767
      Line 105, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_controller_ispr_rdata_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1240):(Time: 4207476 PS + 16) Sampled value (6971756) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_j_cg@4218_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 4227476 PS + 20) Sampled value (6971756) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 4227476 PS + 20) Sampled value (7565921) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 4227476 PS + 20) Sampled value (7565921) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 4237476 PS + 20) Sampled value (7565921) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_b_cg@*_*.mnemonic_cp) is an illegal value. has 1 failures:

  • Test otbn_ctrl_redun has 1 failures.

    • 0.otbn_ctrl_redun.110177920229547781953907165109555276857892636914974901189271975674209590094220
      Line 109, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1158):(Time: 20770188 PS + 19) Sampled value (6450789) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_b_cg@4214_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1564):(Time: 20770188 PS + 19) Sampled value (6450789) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_bxx_cg@4235_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 20832687 PS + 32) Sampled value (6450789) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 20832687 PS + 32) Sampled value (108225364781412) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1122):(Time: 20832687 PS + 32) Sampled value (108225364781412) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_bnxid_cg@4213_1.mnemonic_cp) is an illegal value.
      

• Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 0.chip_tl_errors.92839762528523208866880155993837639049431549427339710746370120253135311431126
      Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

            Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
        UVM_ERROR @ 118.181000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
        UVM_INFO @ 118.181000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:

  • Test chip_rv_dm_lc_disabled has 1 failures.

    • 0.chip_rv_dm_lc_disabled.30152018028664518695845781259918076990277772912830051540988030311520431183659
      Line 216, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

        UVM_ERROR @ 123.233000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40538 read out mismatch
        UVM_INFO @ 123.233000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:

  • Test chip_sw_example_rom has 1 failures.

    • 0.chip_sw_example_rom.34901335635807358598670241319809305206993527549896901875159230039550111624296
      Line 612, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

        UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
        UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 1 failures:

  • Test chip_sw_all_escalation_resets has 1 failures.

    • 0.chip_sw_all_escalation_resets.11116354460850542525507811642142233568528009960577245980394799544980845224536
      Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

        UVM_FATAL @  10.140001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
        UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 1 failures:

  • Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.

    • 0.chip_sw_rstmgr_rst_cnsty_escalation.55784132967959065227663265543837457542574795348149565614717105136371510066447
      Line 479, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

        UVM_ERROR @ 905.702000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
        UVM_INFO @ 905.702000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:

  • Test chip_sw_spi_device_pass_through_collision has 1 failures.

    • 0.chip_sw_spi_device_pass_through_collision.78331859685203401781314513237538538994196458243424304958792933976020532407531
      Line 434, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_ERROR @ 413.248000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
        UVM_INFO @ 413.248000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 1 failures:

  • Test chip_sw_rstmgr_alert_info has 1 failures.

    • 0.chip_sw_rstmgr_alert_info.53896525084611597159901464407418152747566585012510111025401971152357714735202
      Line 449, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

        UVM_ERROR @ 289.958000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
        UVM_INFO @ 289.958000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time! has 1 failures:

  • Test chip_sw_soc_proxy_smoketest has 1 failures.

    • 0.chip_sw_soc_proxy_smoketest.27736814246910708983554577271945259983047801839393839320021533297192889564023
      Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log

        UVM_ERROR @ 137.344000 us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
        UVM_INFO @ 137.344000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:

  • Test chip_sw_soc_proxy_external_wakeup has 1 failures.

    • 0.chip_sw_soc_proxy_external_wakeup.91751690005389873468694435709886508562274112582751347780468689317427797126902
      Line 411, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log

        UVM_ERROR @ 138.824000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
        UVM_INFO @ 138.824000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns * has 1 failures:

  • Test chip_sw_soc_proxy_gpios has 1 failures.

    • 0.chip_sw_soc_proxy_gpios.61770471930568401887816231534126058321640019341949261660709816048264400409547
      Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log

        UVM_ERROR @ 136.474000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
        UVM_INFO @ 136.474000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 1 failures:

  • Test chip_sw_aon_timer_irq has 1 failures.

    • 0.chip_sw_aon_timer_irq.92124788398979684860112239579628878274758908913116839940068816191884883682814
      Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

        UVM_ERROR @ 539.538000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 3980 usec which is not in the range 363 usec and 416 usec
        UVM_INFO @ 539.538000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:

  • Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.

    • 0.chip_sw_aon_timer_wdog_bite_reset.18850566228127235402903031818258629796579856300054695440927840202997486921132
      Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log

        UVM_ERROR @ 164.348000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
        UVM_INFO @ 164.348000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:

  • Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.

    • 0.chip_sw_rv_core_ibex_nmi_irq.39411367929607156089010128576644554278387781081320980473725741745892049039734
      Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log

        UVM_ERROR @ 251.618000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
        UVM_INFO @ 251.618000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:

  • Test chip_sw_kmac_app_rom has 1 failures.

    • 0.chip_sw_kmac_app_rom.5765717025729268561988937985835097356776006427340275419082634940933344425732
      Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log

        UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
        UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:

  • Test chip_sw_dma_abort has 1 failures.

    • 0.chip_sw_dma_abort.90087402213964597867194354142200851960356398765163289543365347857773571913681
      Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

        UVM_FATAL @ 160.288000 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
        UVM_INFO @ 160.288000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:

  • Test chip_padctrl_attributes has 1 failures.

    • 0.chip_padctrl_attributes.78355861325111833920695429706020265126967479154136956895981807431657829686130
      Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.