KMAC/UNMASKED Simulation Results

Wednesday November 12 2025 16:07:41 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	42.83	0.0	2	2	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.42	0.0	2	2	100.00
V1	csr_rw	kmac_csr_rw	1.11	0.0	2	2	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.69	0.0	2	2	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.64	0.0	2	2	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.06	0.0	2	2	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.11	0.0	2	2	100.00
		kmac_csr_aliasing	4.64	0.0	2	2	100.00
V1	mem_walk	kmac_mem_walk	1.03	0.0	2	2	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.35	0.0	2	2	100.00
V1		TOTAL			16	16	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	660.1	0.0	2	2	100.00
V2	burst_write	kmac_burst_write	795.64	0.0	2	2	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.14	0.0	2	2	100.00
		kmac_test_vectors_sha3_256	35.76	0.0	2	2	100.00
		kmac_test_vectors_sha3_384	1386.91	0.0	2	2	100.00
		kmac_test_vectors_sha3_512	1071.68	0.0	2	2	100.00
		kmac_test_vectors_shake_128	2163.63	0.0	2	2	100.00
		kmac_test_vectors_shake_256	283.95	0.0	2	2	100.00
		kmac_test_vectors_kmac	2.44	0.0	2	2	100.00
		kmac_test_vectors_kmac_xof	3.06	0.0	2	2	100.00
V2	sideload	kmac_sideload	294.48	0.0	2	2	100.00
V2	app	kmac_app	159.19	0.0	2	2	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	141.81	0.0	2	2	100.00
V2	entropy_refresh	kmac_entropy_refresh	197.16	0.0	2	2	100.00
V2	error	kmac_error	360.63	0.0	2	2	100.00
V2	key_error	kmac_key_error	7.82	0.0	1	2	50.00
V2	sideload_invalid	kmac_sideload_invalid	1.54	0.0	2	2	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	24.42	0.0	2	2	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	12.84	0.0	2	2	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	46.61	0.0	2	2	100.00
V2	lc_escalation	kmac_lc_escalation	1.88	0.0	2	2	100.00
V2	stress_all	kmac_stress_all	780.45	0.0	2	2	100.00
V2	intr_test	kmac_intr_test	1.1	0.0	2	2	100.00
V2	alert_test	kmac_alert_test	1.11	0.0	2	2	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.5	0.0	2	2	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.5	0.0	2	2	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.42	0.0	2	2	100.00
		kmac_csr_rw	1.11	0.0	2	2	100.00
		kmac_csr_aliasing	4.64	0.0	2	2	100.00
		kmac_same_csr_outstanding	1.55	0.0	2	2	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.42	0.0	2	2	100.00
		kmac_csr_rw	1.11	0.0	2	2	100.00
		kmac_csr_aliasing	4.64	0.0	2	2	100.00
		kmac_same_csr_outstanding	1.55	0.0	2	2	100.00
V2		TOTAL			51	52	98.08
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.04	0.0	2	2	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.04	0.0	2	2	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.04	0.0	2	2	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.04	0.0	2	2	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.66	0.0	2	2	100.00
V2S	tl_intg_err	kmac_sec_cm	43.73	0.0	2	2	100.00
		kmac_tl_intg_err	4.94	0.0	2	2	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.94	0.0	2	2	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.88	0.0	2	2	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	42.83	0.0	2	2	100.00
V2S	sec_cm_key_sideload	kmac_sideload	294.48	0.0	2	2	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.04	0.0	2	2	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	43.73	0.0	2	2	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	43.73	0.0	2	2	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	43.73	0.0	2	2	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	42.83	0.0	2	2	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.88	0.0	2	2	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	43.73	0.0	2	2	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	303.48	0.0	2	2	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	42.83	0.0	2	2	100.00
V2S		TOTAL			10	10	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	41.73	0.0	2	2	100.00
V3		TOTAL			2	2	100.00
	Unmapped tests	rv_dm_smoke	3.28	0.0	1	1	100.00
		rv_dm_tap_fsm	5.07	0.0	0	1	0.00
		rv_dm_sba_tl_access	584.74	0.0	0	1	0.00
		rv_dm_delayed_resp_sba_tl_access	150.76	0.0	0	1	0.00
		rv_dm_bad_sba_tl_access	541.33	0.0	0	1	0.00
		rv_dm_autoincr_sba_tl_access	194.27	0.0	0	1	0.00
		rv_dm_cmderr_busy	0.84	0.0	1	1	100.00
		rv_dm_cmderr_not_supported	1.07	0.0	1	1	100.00
		rv_dm_cmderr_exception	1.43	0.0	1	1	100.00
		rv_dm_mem_tl_access_halted	1.15	0.0	1	1	100.00
		rv_dm_mem_tl_access_resuming	0.73	0.0	0	1	0.00
		rv_dm_hart_unavail	0.79	0.0	0	1	0.00
		rv_dm_cmderr_halt_resume	1.35	0.0	1	1	100.00
		rv_dm_dataaddr_rw_access	0.7	0.0	1	1	100.00
		rv_dm_halt_resume_whereto	0.98	0.0	1	1	100.00
		rv_dm_sba_debug_disabled	1.86	0.0	1	1	100.00
		rv_dm_ndmreset_req	0.78	0.0	1	1	100.00
		rv_dm_jtag_dtm_idle_hint	1.58	0.0	1	1	100.00
		rv_dm_jtag_dmi_dm_inactive	1.43	0.0	1	1	100.00
		rv_dm_jtag_dmi_debug_disabled	0.87	0.0	0	1	0.00
		rv_dm_jtag_dtm_hard_reset	0.82	0.0	1	1	100.00
		rv_dm_abstractcmd_status	0.76	0.0	1	1	100.00
		rv_dm_rom_read_access	0.78	0.0	1	1	100.00
		rv_dm_progbuf_read_write_execute	0.81	0.0	1	1	100.00
		rv_dm_debug_disabled	0.81	0.0	1	1	100.00
		rv_dm_dmi_failed_op	1.66	0.0	1	1	100.00
		rv_dm_hartsel_warl	0.82	0.0	1	1	100.00
		rv_dm_buffered_enable	0.95	0.0	1	1	100.00
		rv_dm_sparse_lc_gate_fsm	0.93	0.0	1	1	100.00
		rv_dm_scanmode	566.0	0.0	0	1	0.00
		rv_dm_stress_all	5340.48	0.0	0	1	0.00
		rv_dm_stress_all_with_rand_reset	0.66	0.0	0	1	0.00
		rv_dm_sec_cm	1.6	0.0	1	1	100.00
		rv_dm_alert_test	0.7	0.0	1	1	100.00
		uart_smoke	1.09	0.0	1	1	100.00
		uart_tx_rx	53.33	0.0	1	1	100.00
		uart_fifo_full	20.84	0.0	1	1	100.00
		uart_fifo_overflow	24.83	0.0	1	1	100.00
		uart_fifo_reset	10.44	0.0	1	1	100.00
		uart_rx_oversample	17.48	0.0	1	1	100.00
		uart_intr	29.44	0.0	1	1	100.00
		uart_noise_filter	2.05	0.0	0	1	0.00
		uart_rx_start_bit_filter	2.14	0.0	1	1	100.00
		uart_rx_parity_err	6.73	0.0	1	1	100.00
		uart_tx_ovrd	2.96	0.0	1	1	100.00
		uart_loopback	6.41	0.0	1	1	100.00
		uart_perf	60.85	0.0	1	1	100.00
		uart_long_xfer_wo_dly	570.79	0.0	1	1	100.00
		uart_stress_all_with_rand_reset	21.76	0.0	1	1	100.00
		uart_stress_all	142.41	0.0	1	1	100.00
		uart_sec_cm	0.78	0.0	1	1	100.00
		uart_alert_test	0.53	0.0	1	1	100.00
		rv_timer_random	0.64	0.0	1	1	100.00
		rv_timer_min	0.51	0.0	1	1	100.00
		rv_timer_max	0.57	0.0	0	1	0.00
		rv_timer_disabled	2.28	0.0	1	1	100.00
		rv_timer_cfg_update_on_fly	184.62	0.0	1	1	100.00
		rv_timer_random_reset	0.6	0.0	0	1	0.00
		rv_timer_stress_all_with_rand_reset	24.17	0.0	1	1	100.00
		rv_timer_stress_all	3.61	0.0	1	1	100.00
		rv_timer_sec_cm	0.87	0.0	1	1	100.00
		rv_timer_alert_test	0.65	0.0	1	1	100.00
		rv_timer_tl_errors	1.43	0.0	1	1	100.00
		rv_timer_tl_intg_err	1.15	0.0	1	1	100.00
		rv_timer_intr_test	0.57	0.0	1	1	100.00
		rv_timer_csr_hw_reset	0.68	0.0	1	1	100.00
		rv_timer_csr_rw	0.54	0.0	1	1	100.00
		rv_timer_csr_bit_bash	1.75	0.0	1	1	100.00
		rv_timer_csr_aliasing	0.68	0.0	1	1	100.00
		rv_timer_same_csr_outstanding	0.72	0.0	1	1	100.00
		rv_timer_csr_mem_rw_with_rand_reset	0.73	0.0	1	1	100.00
		aon_timer_smoke	0.96	0.0	1	1	100.00
		aon_timer_prescaler	67.98	0.0	1	1	100.00
		aon_timer_jump	0.98	0.0	1	1	100.00
		aon_timer_custom_intr	1.32	0.0	1	1	100.00
		aon_timer_smoke_max_thold	1.19	0.0	1	1	100.00
		aon_timer_smoke_min_thold	1.1	0.0	1	1	100.00
		aon_timer_wkup_count_cdc_hi	6.31	0.0	1	1	100.00
		aon_timer_alternating_enable_on_off	9.31	0.0	1	1	100.00
		aon_timer_stress_all_with_rand_reset	13.56	0.0	1	1	100.00
		aon_timer_stress_all	46.32	0.0	1	1	100.00
		aon_timer_sec_cm	3.4	0.0	1	1	100.00
		aon_timer_alert_test	0.89	0.0	1	1	100.00
		aon_timer_tl_errors	1.85	0.0	1	1	100.00
		aon_timer_tl_intg_err	3.06	0.0	1	1	100.00
		aon_timer_intr_test	0.66	0.0	1	1	100.00
		aon_timer_mem_walk	0.58	0.0	1	1	100.00
		aon_timer_mem_partial_access	0.87	0.0	1	1	100.00
		aon_timer_csr_hw_reset	0.83	0.0	1	1	100.00
		aon_timer_csr_rw	0.87	0.0	1	1	100.00
		aon_timer_csr_bit_bash	3.64	0.0	1	1	100.00
		aon_timer_csr_aliasing	0.82	0.0	1	1	100.00
		aon_timer_same_csr_outstanding	0.95	0.0	1	1	100.00
		aon_timer_csr_mem_rw_with_rand_reset	0.98	0.0	1	1	100.00
		spi_device_csb_read	0.7	0.0	1	1	100.00
		spi_device_mem_parity	0.68	0.0	0	1	0.00
		spi_device_ram_cfg	0.66	0.0	0	1	0.00
		spi_device_tpm_read_hw_reg	3.9	0.0	1	1	100.00
		spi_device_tpm_all	5.07	0.0	1	1	100.00
		spi_device_tpm_sts_read	0.8	0.0	1	1	100.00
		spi_device_tpm_rw	0.74	0.0	1	1	100.00
		spi_device_pass_cmd_filtering	1.61	0.0	1	1	100.00
		spi_device_pass_addr_payload_swap	3.11	0.0	1	1	100.00
		spi_device_intercept	3.4	0.0	1	1	100.00
		spi_device_mailbox	1.76	0.0	1	1	100.00
		spi_device_upload	9.12	0.0	1	1	100.00
		spi_device_cfg_cmd	8.21	0.0	1	1	100.00
		spi_device_flash_mode	15.23	0.0	1	1	100.00
		spi_device_flash_mode_ignore_cmds	23.38	0.0	1	1	100.00
		spi_device_read_buffer_direct	2.51	0.0	1	1	100.00
		spi_device_flash_all	30.1	0.0	1	1	100.00
		spi_device_flash_and_tpm	6.27	0.0	1	1	100.00
		spi_device_flash_and_tpm_min_idle	26.45	0.0	1	1	100.00
		spi_device_stress_all	78.04	0.0	1	1	100.00
		spi_device_sec_cm	0.83	0.0	1	1	100.00
		spi_device_alert_test	0.71	0.0	1	1	100.00
		spi_device_tl_errors	3.81	0.0	1	1	100.00
		spi_device_tl_intg_err	14.71	0.0	1	1	100.00
		spi_device_intr_test	0.7	0.0	1	1	100.00
		spi_device_mem_walk	0.67	0.0	1	1	100.00
		spi_device_mem_partial_access	1.0	0.0	1	1	100.00
		spi_device_csr_hw_reset	0.93	0.0	1	1	100.00
		spi_device_csr_rw	1.07	0.0	1	1	100.00
		spi_device_csr_bit_bash	8.29	0.0	1	1	100.00
		spi_device_csr_aliasing	5.54	0.0	1	1	100.00
		spi_device_same_csr_outstanding	1.36	0.0	1	1	100.00
		spi_device_csr_mem_rw_with_rand_reset	1.77	0.0	1	1	100.00
		prim_lfsr_gal_test	154.76	0.0	1	1	100.00
		prim_lfsr_fib_test	157.59	0.0	1	1	100.00
		prim_lfsr_fib_smoke	1.36	0.0	1	1	100.00
		prim_lfsr_gal_smoke	1.31	0.0	1	1	100.00
		keymgr_smoke	1.6	0.0	1	1	100.00
		keymgr_sideload	2.19	0.0	1	1	100.00
		keymgr_sideload_kmac	13.2	0.0	1	1	100.00
		keymgr_sideload_aes	15.72	0.0	1	1	100.00
		keymgr_sideload_otbn	13.43	0.0	1	1	100.00
		keymgr_random	5.55	0.0	1	1	100.00
		keymgr_cfg_regwen	2.31	0.0	1	1	100.00
		keymgr_direct_to_disabled	1.89	0.0	1	1	100.00
		keymgr_lc_disable	11.92	0.0	1	1	100.00
		keymgr_sw_invalid_input	2.36	0.0	1	1	100.00
		keymgr_hwsw_invalid_input	3.26	0.0	1	1	100.00
		keymgr_kmac_rsp_err	2.73	0.0	1	1	100.00
		keymgr_custom_cm	4.58	0.0	1	1	100.00
		keymgr_sideload_protect	2.53	0.0	1	1	100.00
		keymgr_sync_async_fault_cross	1.81	0.0	1	1	100.00
		keymgr_stress_all	27.51	0.0	1	1	100.00
		keymgr_stress_all_with_rand_reset	3.91	0.0	1	1	100.00
		keymgr_sec_cm	13.9	0.0	1	1	100.00
		keymgr_alert_test	0.79	0.0	1	1	100.00
		keymgr_shadow_reg_errors	2.4	0.0	1	1	100.00
		keymgr_shadow_reg_errors_with_csr_rw	7.49	0.0	1	1	100.00
		keymgr_tl_errors	1.74	0.0	1	1	100.00
		keymgr_tl_intg_err	3.0	0.0	1	1	100.00
		keymgr_intr_test	0.87	0.0	1	1	100.00
		keymgr_csr_hw_reset	1.2	0.0	1	1	100.00
		keymgr_csr_rw	0.86	0.0	1	1	100.00
		keymgr_csr_bit_bash	4.28	0.0	1	1	100.00
		keymgr_csr_aliasing	4.98	0.0	1	1	100.00
		keymgr_same_csr_outstanding	1.27	0.0	1	1	100.00
		keymgr_csr_mem_rw_with_rand_reset	1.37	0.0	1	1	100.00
		rstmgr_smoke	1.14	0.0	1	1	100.00
		rstmgr_por_stretcher	1.43	0.0	1	1	100.00
		rstmgr_reset	5.11	0.0	1	1	100.00
		rstmgr_sw_rst_reset_race	0.78	0.0	1	1	100.00
		rstmgr_sw_rst	0.9	0.0	1	1	100.00
		rstmgr_sec_cm_scan_intersig_mubi	1.08	0.0	1	1	100.00
		rstmgr_leaf_rst_cnsty	3.46	0.0	1	1	100.00
		rstmgr_leaf_rst_shadow_attack	1.95	0.0	1	1	100.00
		rstmgr_stress_all	14.08	0.0	1	1	100.00
		rstmgr_sec_cm	30.72	0.0	1	1	100.00
		rstmgr_alert_test	0.78	0.0	1	1	100.00
		rstmgr_tl_errors	1.27	0.0	1	1	100.00
		rstmgr_tl_intg_err	3.82	0.0	1	1	100.00
		rstmgr_csr_hw_reset	0.89	0.0	1	1	100.00
		rstmgr_csr_rw	0.82	0.0	1	1	100.00
		rstmgr_csr_bit_bash	3.77	0.0	1	1	100.00
		rstmgr_csr_aliasing	1.31	0.0	1	1	100.00
		rstmgr_same_csr_outstanding	0.92	0.0	1	1	100.00
		rstmgr_csr_mem_rw_with_rand_reset	1.05	0.0	1	1	100.00
		sram_ctrl_smoke	16.57	0.0	2	2	100.00
		sram_ctrl_multiple_keys	870.41	0.0	2	2	100.00
		sram_ctrl_bijection	1421.24	0.0	2	2	100.00
		sram_ctrl_stress_pipeline	206.43	0.0	2	2	100.00
		sram_ctrl_partial_access	12.04	0.0	2	2	100.00
		sram_ctrl_partial_access_b2b	302.52	0.0	2	2	100.00
		sram_ctrl_max_throughput	29.12	0.0	2	2	100.00
		sram_ctrl_throughput_w_partial_write	48.65	0.0	2	2	100.00
		sram_ctrl_throughput_w_readback	6.7	0.0	2	2	100.00
		sram_ctrl_lc_escalation	56.97	0.0	2	2	100.00
		sram_ctrl_access_during_key_req	687.49	0.0	2	2	100.00
		sram_ctrl_executable	316.57	0.0	2	2	100.00
		sram_ctrl_regwen	374.45	0.0	2	2	100.00
		sram_ctrl_ram_cfg	2.26	0.0	2	2	100.00
		sram_ctrl_mem_walk	142.15	0.0	2	2	100.00
		sram_ctrl_mem_partial_access	53.66	0.0	2	2	100.00
		sram_ctrl_readback_err	4.49	0.0	1	2	50.00
		sram_ctrl_mubi_enc_err	3.77	0.0	2	2	100.00
		sram_ctrl_stress_all_with_rand_reset	150.57	0.0	2	2	100.00
		sram_ctrl_stress_all	1699.07	0.0	2	2	100.00
		sram_ctrl_sec_cm	1.07	0.0	0	2	0.00
		sram_ctrl_alert_test	0.84	0.0	2	2	100.00
		sram_ctrl_passthru_mem_tl_intg_err	17.55	0.0	2	2	100.00
		sram_ctrl_tl_errors	3.43	0.0	2	2	100.00
		sram_ctrl_tl_intg_err	2.53	0.0	2	2	100.00
		sram_ctrl_csr_hw_reset	0.88	0.0	2	2	100.00
		sram_ctrl_csr_rw	0.91	0.0	2	2	100.00
		sram_ctrl_csr_bit_bash	2.17	0.0	2	2	100.00
		sram_ctrl_csr_aliasing	0.9	0.0	2	2	100.00
		sram_ctrl_same_csr_outstanding	0.87	0.0	2	2	100.00
		sram_ctrl_csr_mem_rw_with_rand_reset	2.64	0.0	2	2	100.00
		alert_handler_shadow_reg_errors_with_csr_rw	730.74	0.0	1	1	100.00
		alert_handler_shadow_reg_errors	85.07	0.0	1	1	100.00
		alert_handler_tl_errors	13.52	0.0	1	1	100.00
		alert_handler_tl_intg_err	29.36	0.0	1	1	100.00
		alert_handler_intr_test	1.52	0.0	1	1	100.00
		alert_handler_csr_hw_reset	6.38	0.0	1	1	100.00
		alert_handler_csr_rw	4.89	0.0	1	1	100.00
		alert_handler_csr_bit_bash	186.19	0.0	1	1	100.00
		alert_handler_csr_aliasing	92.85	0.0	1	1	100.00
		alert_handler_same_csr_outstanding	13.78	0.0	1	1	100.00
		alert_handler_csr_mem_rw_with_rand_reset	5.87	0.0	1	1	100.00
		prim_present_test	22.65	0.0	1	1	100.00
		rv_dm_csr_aliasing	44.29	0.0	1	1	100.00
		rv_dm_jtag_dtm_csr_hw_reset	1.16	0.0	1	1	100.00
		rv_dm_jtag_dtm_csr_rw	1.22	0.0	1	1	100.00
		rv_dm_jtag_dtm_csr_bit_bash	15.65	0.0	1	1	100.00
		rv_dm_jtag_dtm_csr_aliasing	1.37	0.0	1	1	100.00
		rv_dm_jtag_dmi_csr_hw_reset	7.99	0.0	1	1	100.00
		rv_dm_jtag_dmi_csr_rw	6.16	0.0	1	1	100.00
		rv_dm_jtag_dmi_csr_bit_bash	3.31	0.0	1	1	100.00
		rv_dm_jtag_dmi_csr_aliasing	26.93	0.0	1	1	100.00
		rv_dm_tap_fsm_rand_reset	0.85	0.0	0	1	0.00
		rv_dm_tl_errors	0.96	0.0	0	1	0.00
		rv_dm_tl_intg_err	8.19	0.0	1	1	100.00
		rv_dm_mem_walk	1.07	0.0	1	1	100.00
		rv_dm_mem_partial_access	0.96	0.0	1	1	100.00
		rv_dm_csr_hw_reset	2.23	0.0	1	1	100.00
		rv_dm_csr_rw	1.92	0.0	1	1	100.00
		rv_dm_csr_bit_bash	51.15	0.0	1	1	100.00
		rv_dm_same_csr_outstanding	4.41	0.0	1	1	100.00
		rv_dm_csr_mem_rw_with_rand_reset	0.96	0.0	0	1	0.00
		rstmgr_cnsty_chk_test	2.18	0.0	1	1	100.00
		uart_tl_errors	1.8	0.0	1	1	100.00
		uart_tl_intg_err	1.09	0.0	1	1	100.00
		uart_intr_test	0.74	0.0	1	1	100.00
		uart_csr_hw_reset	0.63	0.0	1	1	100.00
		uart_csr_rw	0.77	0.0	1	1	100.00
		uart_csr_bit_bash	1.24	0.0	1	1	100.00
		uart_csr_aliasing	0.64	0.0	1	1	100.00
		uart_same_csr_outstanding	0.88	0.0	1	1	100.00
		uart_csr_mem_rw_with_rand_reset	0.99	0.0	1	1	100.00
		prim_esc_test	0.5	0.0	1	1	100.00
		xbar_smoke	8.14	0.0	5	5	100.00
		xbar_smoke_zero_delays	9.05	0.0	5	5	100.00
		xbar_smoke_large_delays	259.03	0.0	5	5	100.00
		xbar_smoke_slow_rsp	423.67	0.0	5	5	100.00
		xbar_random	174.69	0.0	5	5	100.00
		xbar_random_zero_delays	88.68	0.0	5	5	100.00
		xbar_random_large_delays	763.97	0.0	5	5	100.00
		xbar_random_slow_rsp	1274.56	0.0	5	5	100.00
		xbar_access_same_device	273.89	0.0	5	5	100.00
		xbar_access_same_device_slow_rsp	1153.72	0.0	5	5	100.00
		xbar_same_source	147.04	0.0	5	5	100.00
		xbar_error_random	182.2	0.0	5	5	100.00
		xbar_unmapped_addr	83.17	0.0	5	5	100.00
		xbar_error_and_unmapped_addr	45.44	0.0	5	5	100.00
		xbar_stress_all	658.31	0.0	5	5	100.00
		xbar_stress_all_with_rand_reset	2255.01	0.0	5	5	100.00
		xbar_stress_all_with_error	505.56	0.0	5	5	100.00
		xbar_stress_all_with_reset_error	902.67	0.0	5	5	100.00
		keymgr_dpe_smoke	12.93	0.0	1	1	100.00
		keymgr_dpe_sec_cm	19.26	0.0	1	1	100.00
		keymgr_dpe_alert_test	0.89	0.0	1	1	100.00
		keymgr_dpe_shadow_reg_errors	3.36	0.0	1	1	100.00
		keymgr_dpe_shadow_reg_errors_with_csr_rw	2.83	0.0	1	1	100.00
		keymgr_dpe_tl_errors	2.79	0.0	1	1	100.00
		keymgr_dpe_tl_intg_err	4.01	0.0	1	1	100.00
		keymgr_dpe_intr_test	0.97	0.0	1	1	100.00
		keymgr_dpe_csr_hw_reset	0.92	0.0	1	1	100.00
		keymgr_dpe_csr_rw	1.05	0.0	1	1	100.00
		keymgr_dpe_csr_bit_bash	8.57	0.0	1	1	100.00
		keymgr_dpe_csr_aliasing	4.77	0.0	1	1	100.00
		keymgr_dpe_same_csr_outstanding	1.9	0.0	1	1	100.00
		keymgr_dpe_csr_mem_rw_with_rand_reset	1.19	0.0	1	1	100.00
		clkmgr_smoke	1.19	0.0	1	1	100.00
		clkmgr_frequency	0.77	0.0	0	1	0.00
		clkmgr_frequency_timeout	0.7	0.0	0	1	0.00
		clkmgr_peri	1.0	0.0	1	1	100.00
		clkmgr_trans	1.26	0.0	1	1	100.00
		clkmgr_clk_status	1.44	0.0	1	1	100.00
		clkmgr_idle_intersig_mubi	4.98	0.0	1	1	100.00
		clkmgr_regwen	0.75	0.0	0	1	0.00
		clkmgr_sec_cm	4.78	0.0	1	1	100.00
		clkmgr_stress_all_with_rand_reset	0.87	0.0	0	1	0.00
		clkmgr_stress_all	1.09	0.0	0	1	0.00
		clkmgr_alert_test	1.61	0.0	1	1	100.00
		clkmgr_shadow_reg_errors	1.34	0.0	1	1	100.00
		clkmgr_shadow_reg_errors_with_csr_rw	0.92	0.0	0	1	0.00
		clkmgr_tl_errors	2.83	0.0	1	1	100.00
		clkmgr_tl_intg_err	0.61	0.0	0	1	0.00
		clkmgr_csr_hw_reset	0.84	0.0	1	1	100.00
		clkmgr_csr_rw	1.06	0.0	1	1	100.00
		clkmgr_csr_bit_bash	0.61	0.0	0	1	0.00
		clkmgr_csr_aliasing	1.03	0.0	0	1	0.00
		clkmgr_same_csr_outstanding	0.78	0.0	0	1	0.00
		clkmgr_csr_mem_rw_with_rand_reset	1.19	0.0	0	1	0.00
		i2c_host_smoke	40.95	0.0	1	1	100.00
		i2c_host_override	0.7	0.0	1	1	100.00
		i2c_host_fifo_watermark	113.63	0.0	1	1	100.00
		i2c_host_fifo_overflow	27.43	0.0	1	1	100.00
		i2c_host_fifo_reset_fmt	1.06	0.0	1	1	100.00
		i2c_host_fifo_fmt_empty	2.52	0.0	1	1	100.00
		i2c_host_fifo_reset_rx	3.03	0.0	1	1	100.00
		i2c_host_fifo_full	56.5	0.0	1	1	100.00
		i2c_host_perf	8.31	0.0	1	1	100.00
		i2c_host_perf_precise	2.81	0.0	1	1	100.00
		i2c_host_stretch_timeout	9.5	0.0	1	1	100.00
		i2c_host_error_intr	1.55	0.0	0	1	0.00
		i2c_host_stress_all	498.5400000000001	0.0	1	1	100.00
		i2c_target_glitch	1.78	0.0	0	1	0.00
		i2c_target_smoke	12.83	0.0	1	1	100.00
		i2c_target_stress_wr	148.01	0.0	1	1	100.00
		i2c_target_stress_rd	9.56	0.0	1	1	100.00
		i2c_target_stretch	11.35	0.0	1	1	100.00
		i2c_target_intr_smoke	3.74	0.0	1	1	100.00
		i2c_target_intr_stress_wr	80.37	0.0	1	1	100.00
		i2c_target_timeout	4.72	0.0	1	1	100.00
		i2c_target_unexp_stop	1.27	0.0	0	1	0.00
		i2c_target_fifo_reset_acq	0.96	0.0	1	1	100.00
		i2c_target_fifo_reset_tx	1.06	0.0	1	1	100.00
		i2c_target_perf	4.75	0.0	1	1	100.00
		i2c_target_stress_all	375.39	0.0	1	1	100.00
		i2c_target_bad_addr	4.56	0.0	1	1	100.00
		i2c_target_hrst	2.37	0.0	1	1	100.00
		i2c_host_stress_all_with_rand_reset	3.48	0.0	0	1	0.00
		i2c_target_stress_all_with_rand_reset	12.85	0.0	0	1	0.00
		i2c_host_mode_toggle	0.73	0.0	0	1	0.00
		i2c_host_may_nack	15.27	0.0	1	1	100.00
		i2c_target_fifo_watermarks_acq	1.8	0.0	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.02	0.0	1	1	100.00
		i2c_target_tx_stretch_ctrl	2.53	0.0	1	1	100.00
		i2c_target_smbus_maxlen	1.79	0.0	1	1	100.00
		i2c_target_nack_acqfull	2.98	0.0	1	1	100.00
		i2c_target_nack_acqfull_addr	1.73	0.0	1	1	100.00
		i2c_target_nack_txstretch	1.21	0.0	0	1	0.00
		i2c_sec_cm	1.02	0.0	1	1	100.00
		i2c_alert_test	0.76	0.0	1	1	100.00
		i2c_tl_errors	1.32	0.0	1	1	100.00
		i2c_tl_intg_err	1.63	0.0	1	1	100.00
		i2c_intr_test	0.98	0.0	1	1	100.00
		i2c_csr_hw_reset	0.82	0.0	1	1	100.00
		i2c_csr_rw	0.71	0.0	1	1	100.00
		i2c_csr_bit_bash	3.24	0.0	1	1	100.00
		i2c_csr_aliasing	1.12	0.0	1	1	100.00
		i2c_same_csr_outstanding	0.91	0.0	1	1	100.00
		i2c_csr_mem_rw_with_rand_reset	0.93	0.0	1	1	100.00
		prim_async_alert	0.51	0.0	1	1	100.00
		prim_async_fatal_alert	0.67	0.0	1	1	100.00
		prim_async_fatal_alert_with_3_cycles_skew	0.52	0.0	1	1	100.00
		prim_sync_alert	0.47	0.0	1	1	100.00
		alert_handler_smoke	26.17	0.0	1	1	100.00
		alert_handler_random_alerts	8.04	0.0	1	1	100.00
		alert_handler_random_classes	15.11	0.0	1	1	100.00
		alert_handler_esc_intr_timeout	28.13	0.0	1	1	100.00
		alert_handler_esc_alert_accum	205.49	0.0	1	1	100.00
		alert_handler_sig_int_fail	7.62	0.0	1	1	100.00
		alert_handler_entropy	2178.43	0.0	1	1	100.00
		alert_handler_ping_timeout	7.63	0.0	0	1	0.00
		alert_handler_lpg	19.29	0.0	0	1	0.00
		alert_handler_lpg_stub_clk	1910.19	0.0	1	1	100.00
		alert_handler_entropy_stress	59.53	0.0	1	1	100.00
		alert_handler_stress_all	251.42	0.0	1	1	100.00
		alert_handler_alert_accum_saturation	3.19	0.0	1	1	100.00
		alert_handler_stress_all_with_rand_reset	328.79	0.0	0	1	0.00
		alert_handler_sec_cm	19.29	0.0	1	1	100.00
		spi_host_tl_errors	11.0	129.826073	1	1	100.00
		spi_host_tl_intg_err	8.0	216.25530600000002	1	1	100.00
		spi_host_intr_test	9.0	17.395809	1	1	100.00
		spi_host_mem_walk	9.0	16.160176	1	1	100.00
		spi_host_mem_partial_access	5.0	86.447848	1	1	100.00
		spi_host_csr_hw_reset	3.0	59.290997000000004	1	1	100.00
		spi_host_csr_rw	1.0	20.339509999999997	1	1	100.00
		spi_host_csr_bit_bash	2.0	39.106178	1	1	100.00
		spi_host_csr_aliasing	1.0	44.547754999999995	1	1	100.00
		spi_host_same_csr_outstanding	1.0	29.149894	1	1	100.00
		spi_host_csr_mem_rw_with_rand_reset	1.0	62.334759	1	1	100.00
		mbx_smoke	76.0	7393.01878	1	1	100.00
		mbx_stress	22.0	3607.265364	1	1	100.00
		mbx_stress_zero_delays	50.0	4507.012078	1	1	100.00
		mbx_imbx_oob	2.0	190.411537	0	1	0.00
		mbx_doe_intr_msg	19.0	836.349961	1	1	100.00
		mbx_sec_cm	2.0	54.973028	1	1	100.00
		mbx_alert_test	1.0	26.35124	1	1	100.00
		mbx_tl_errors	1.0	50.830599	1	1	100.00
		mbx_tl_intg_err	1.0	665.276057	1	1	100.00
		mbx_intr_test	2.0	47.027483000000004	1	1	100.00
		mbx_csr_hw_reset	2.0	65.90950199999999	1	1	100.00
		mbx_csr_rw	1.0	13.698872999999999	1	1	100.00
		mbx_csr_bit_bash	2.0	146.018418	1	1	100.00
		mbx_csr_aliasing	1.0	19.741885	1	1	100.00
		mbx_same_csr_outstanding	1.0	41.529642	1	1	100.00
		mbx_csr_mem_rw_with_rand_reset	2.0	189.75080799999998	1	1	100.00
		spi_host_smoke	63.0	16856.921421	1	1	100.00
		spi_host_speed	4.0	105.502736	1	1	100.00
		spi_host_upper_range_clkdiv	239.0	45598.532218	1	1	100.00
		spi_host_performance	2.0	31.435079	1	1	100.00
		spi_host_sw_reset	2.0	35.190875	1	1	100.00
		spi_host_overflow_underflow	4.0	1074.556675	1	1	100.00
		spi_host_error_cmd	2.0	19.404080999999998	1	1	100.00
		spi_host_event	27.0	3744.0603480000004	1	1	100.00
		spi_host_passthrough_mode	1.0	86.428308	1	1	100.00
		spi_host_status_stall	44.0	10701.297254000001	1	1	100.00
		spi_host_idlecsbactive	2.0	78.072661	1	1	100.00
		spi_host_stress_all	17.0	514.554932	1	1	100.00
		spi_host_spien	3.0	3948.326375	1	1	100.00
		spi_host_sec_cm	2.0	243.345071	1	1	100.00
		spi_host_alert_test	2.0	18.175738000000003	1	1	100.00
		ac_range_check_smoke	31.0	4831.403221	1	1	100.00
		ac_range_check_smoke_racl	33.0	663.118563	1	1	100.00
		ac_range_check_smoke_high_threshold	26.0	1299.842535	1	1	100.00
		ac_range_check_bypass	37.0	3319.626417	1	1	100.00
		ac_range_check_lock_range	4.0	202.30838699999998	1	1	100.00
		ac_range_check_stress_all_with_rand_reset	219.0	389.414289	1	1	100.00
		ac_range_check_stress_all	119.0	9471.861106	0	1	0.00
		ac_range_check_sec_cm	2.0	33.854867	1	1	100.00
		ac_range_check_alert_test	1.0	39.695409	1	1	100.00
		ac_range_check_tl_errors	3.0	184.88709	1	1	100.00
		ac_range_check_tl_intg_err	6.0	113.083178	1	1	100.00
		ac_range_check_shadow_reg_errors	17.0	1019.774585	1	1	100.00
		ac_range_check_shadow_reg_errors_with_csr_rw	67.0	5550.422071999999	1	1	100.00
		ac_range_check_intr_test	2.0	13.039952999999999	1	1	100.00
		ac_range_check_csr_hw_reset	2.0	210.996006	1	1	100.00
		ac_range_check_csr_rw	2.0	39.488282	1	1	100.00
		ac_range_check_csr_bit_bash	35.0	2705.311698	1	1	100.00
		ac_range_check_csr_aliasing	22.0	1469.229037	1	1	100.00
		ac_range_check_same_csr_outstanding	4.0	150.50687	1	1	100.00
		ac_range_check_csr_mem_rw_with_rand_reset	3.0	44.160553	1	1	100.00
		prim_sync_fatal_alert	0.7	0.0	1	1	100.00
		prim_prince_test	10.27	0.0	1	1	100.00
		tl_agent_smoke	0.88	0.0	1	1	100.00
		dma_generic_smoke	5.0	326.197522	1	1	100.00
		dma_memory_smoke	6.0	1323.550911	1	1	100.00
		dma_handshake_smoke	6.0	2248.592063	1	1	100.00
		dma_memory_region_lock	36.0	21289.84116	1	1	100.00
		dma_abort	5.0	724.385532	1	1	100.00
		dma_short_transfer	94.0	5456.988042999999	1	1	100.00
		dma_longer_transfer	5.0	848.7702290000001	1	1	100.00
		dma_mem_enabled	16.0	199.950215	1	1	100.00
		dma_config_lock	8.0	322.410974	1	1	100.00
		dma_generic_stress	1116.0	876737.090909	1	1	100.00
		dma_memory_stress	829.0	79052.831175	1	1	100.00
		dma_handshake_stress	446.0	162816.17759200002	1	1	100.00
		dma_stress_all	266.0	41337.970931	1	1	100.00
		dma_stress_all_with_rand_reset	12.0	1092.0002860000002	0	1	0.00
		dma_sec_cm	1.0	10.877934	1	1	100.00
		dma_alert_test	1.0	35.087688	1	1	100.00
		dma_tl_errors	2.0	165.07749900000002	1	1	100.00
		dma_tl_intg_err	4.0	688.486838	1	1	100.00
		dma_intr_test	1.0	44.603521	1	1	100.00
		dma_csr_hw_reset	2.0	30.819046	1	1	100.00
		dma_csr_rw	1.0	22.653111	1	1	100.00
		dma_csr_bit_bash	9.0	1033.492518	1	1	100.00
		dma_csr_aliasing	3.0	83.521423	1	1	100.00
		dma_same_csr_outstanding	2.0	40.688417	1	1	100.00
		dma_csr_mem_rw_with_rand_reset	1.0	78.13781399999999	1	1	100.00
		aes_tl_errors	3.0	131.748424	2	2	100.00
		aes_tl_intg_err	3.0	173.832491	2	2	100.00
		aes_shadow_reg_errors	2.0	77.363337	2	2	100.00
		aes_shadow_reg_errors_with_csr_rw	2.0	234.500149	2	2	100.00
		aes_csr_hw_reset	2.0	58.206156	2	2	100.00
		aes_csr_rw	2.0	70.291315	2	2	100.00
		aes_csr_bit_bash	7.0	3197.452072	2	2	100.00
		aes_csr_aliasing	3.0	536.062706	2	2	100.00
		aes_same_csr_outstanding	3.0	357.778952	2	2	100.00
		aes_csr_mem_rw_with_rand_reset	2.0	66.624466	2	2	100.00
		aes_wake_up	3.0	187.402114	2	2	100.00
		aes_nist_vectors	9.0	3720.970237	2	2	100.00
		aes_deinit	3.0	110.05380000000001	2	2	100.00
		aes_man_cfg_err	2.0	54.303815	2	2	100.00
		aes_readability	2.0	86.01961	2	2	100.00
		aes_smoke	4.0	258.472595	2	2	100.00
		aes_config_error	3.0	96.09204700000001	2	2	100.00
		aes_stress	23.0	2538.239145	2	2	100.00
		aes_b2b	4.0	93.836691	2	2	100.00
		aes_clear	5.0	155.21151	2	2	100.00
		aes_alert_reset	2.0	81.984792	2	2	100.00
		aes_sideload	3.0	89.217333	2	2	100.00
		aes_reseed	5.0	192.284768	2	2	100.00
		aes_fi	3.0	233.104703	2	2	100.00
		aes_control_fi	2.0	63.086446	2	2	100.00
		aes_cipher_fi	2.0	47.591247	2	2	100.00
		aes_ctr_fi	2.0	64.812076	2	2	100.00
		aes_core_fi	2.0	75.695164	2	2	100.00
		aes_stress_all	16.0	712.375284	2	2	100.00
		aes_stress_all_with_rand_reset	7.0	411.84366700000004	0	2	0.00
		aes_sec_cm	8.0	1318.126553	2	2	100.00
		aes_alert_test	2.0	141.833511	2	2	100.00
		csrng_tl_errors	3.0	98.383278	1	1	100.00
		csrng_tl_intg_err	3.0	97.162155	1	1	100.00
		csrng_intr_test	2.0	13.688012	1	1	100.00
		csrng_csr_hw_reset	3.0	61.961974999999995	1	1	100.00
		csrng_csr_rw	2.0	68.228828	1	1	100.00
		csrng_csr_bit_bash	19.0	1094.1122560000001	1	1	100.00
		csrng_csr_aliasing	4.0	157.15994	1	1	100.00
		csrng_same_csr_outstanding	2.0	25.405527999999997	1	1	100.00
		csrng_csr_mem_rw_with_rand_reset	2.0	38.708271	1	1	100.00
		gpio_csr_rw	1.04	0.0	1	1	100.00
		gpio_same_csr_outstanding	1.06	0.0	1	1	100.00
		gpio_csr_aliasing	1.16	0.0	1	1	100.00
		gpio_csr_mem_rw_with_rand_reset	0.98	0.0	1	1	100.00
		gpio_tl_intg_err	1.38	0.0	1	1	100.00
		gpio_tl_errors	1.4	0.0	1	1	100.00
		gpio_intr_test	0.71	0.0	1	1	100.00
		gpio_csr_hw_reset	0.73	0.0	1	1	100.00
		gpio_csr_bit_bash	2.47	0.0	1	1	100.00
		csrng_smoke	2.0	24.335488	1	1	100.00
		csrng_cmds	89.0	4113.846542	1	1	100.00
		csrng_stress_all	837.0	53767.079055	1	1	100.00
		csrng_intr	5.0	84.800609	1	1	100.00
		csrng_alert	8.0	475.830769	1	1	100.00
		csrng_err	3.0	21.242097	1	1	100.00
		csrng_regwen	2.0	21.025862	1	1	100.00
		csrng_stress_all_with_rand_reset	69.0	1298.9535079999998	1	1	100.00
		csrng_sec_cm	3.0	262.3892	1	1	100.00
		csrng_alert_test	3.0	54.452487999999995	1	1	100.00
		gpio_smoke	1.52	0.0	1	1	100.00
		gpio_smoke_no_pullup_pulldown	1.27	0.0	1	1	100.00
		gpio_inp_prd_cnt	0.83	0.0	1	1	100.00
		gpio_random_dout_din	1.63	0.0	1	1	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.37	0.0	1	1	100.00
		gpio_dout_din_regs_random_rw	0.9	0.0	1	1	100.00
		gpio_intr_rand_pgm	1.25	0.0	1	1	100.00
		gpio_rand_intr_trigger	2.7	0.0	1	1	100.00
		gpio_intr_with_filter_rand_intr_event	1.26	0.0	1	1	100.00
		gpio_filter_stress	12.84	0.0	1	1	100.00
		gpio_random_long_reg_writes_reg_reads	2.79	0.0	1	1	100.00
		gpio_full_random	1.06	0.0	1	1	100.00
		gpio_stress_all	80.87	0.0	1	1	100.00
		gpio_stress_all_with_rand_reset	12.24	0.0	0	1	0.00
		gpio_rand_straps	0.7	0.0	1	1	100.00
		gpio_sec_cm	1.08	0.0	1	1	100.00
		gpio_alert_test	0.69	0.0	1	1	100.00
		gpio_smoke_en_cdc_prim	1.0	0.0	1	1	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.21	0.0	1	1	100.00
		hmac_tl_errors	3.34	0.0	1	1	100.00
		hmac_tl_intg_err	2.6	0.0	1	1	100.00
		hmac_intr_test	0.69	0.0	1	1	100.00
		hmac_csr_hw_reset	0.9	0.0	1	1	100.00
		hmac_csr_rw	1.15	0.0	1	1	100.00
		hmac_csr_bit_bash	3.64	0.0	1	1	100.00
		hmac_csr_aliasing	6.21	0.0	1	1	100.00
		hmac_same_csr_outstanding	2.65	0.0	1	1	100.00
		hmac_csr_mem_rw_with_rand_reset	1.16	0.0	1	1	100.00
		hmac_smoke	12.77	0.0	1	1	100.00
		hmac_long_msg	31.71	0.0	1	1	100.00
		hmac_stress_reset	5.21	0.0	1	1	100.00
		hmac_back_pressure	49.52	0.0	1	1	100.00
		hmac_datapath_stress	440.84	0.0	1	1	100.00
		hmac_burst_wr	9.32	0.0	1	1	100.00
		hmac_error	44.79	0.0	1	1	100.00
		hmac_wipe_secret	64.36	0.0	1	1	100.00
		hmac_test_sha256_vectors	9.61	0.0	1	1	100.00
		hmac_test_sha384_vectors	391.16	0.0	1	1	100.00
		hmac_test_sha512_vectors	348.14	0.0	1	1	100.00
		hmac_test_hmac256_vectors	9.08	0.0	1	1	100.00
		hmac_test_hmac384_vectors	10.86	0.0	1	1	100.00
		hmac_test_hmac512_vectors	11.4	0.0	1	1	100.00
		hmac_stress_all	997.0399999999998	0.0	1	1	100.00
		hmac_stress_all_with_rand_reset	178.19	0.0	1	1	100.00
		hmac_directed	1.29	0.0	1	1	100.00
		hmac_sec_cm	1.23	0.0	1	1	100.00
		hmac_alert_test	0.8	0.0	1	1	100.00
		edn_tl_errors	2.18	0.0	1	1	100.00
		edn_tl_intg_err	2.08	0.0	1	1	100.00
		edn_intr_test	1.06	0.0	1	1	100.00
		edn_csr_hw_reset	0.91	0.0	1	1	100.00
		edn_csr_rw	0.9	0.0	1	1	100.00
		edn_csr_bit_bash	4.28	0.0	1	1	100.00
		edn_csr_aliasing	1.23	0.0	1	1	100.00
		edn_same_csr_outstanding	0.98	0.0	1	1	100.00
		edn_csr_mem_rw_with_rand_reset	1.62	0.0	1	1	100.00
		edn_smoke	1.12	0.0	1	1	100.00
		edn_regwen	1.08	0.0	1	1	100.00
		edn_genbits	1.24	0.0	1	1	100.00
		edn_stress_all	1.92	0.0	1	1	100.00
		edn_stress_all_with_rand_reset	50.15	0.0	1	1	100.00
		edn_intr	1.25	0.0	1	1	100.00
		edn_alert	1.48	0.0	1	1	100.00
		edn_err	1.08	0.0	1	1	100.00
		edn_disable	0.89	0.0	1	1	100.00
		edn_disable_auto_req_mode	1.19	0.0	1	1	100.00
		edn_sec_cm	3.74	0.0	1	1	100.00
		edn_alert_test	1.37	0.0	1	1	100.00
		lc_ctrl_jtag_csr_hw_reset	5.6	0.0	2	2	100.00
		lc_ctrl_jtag_csr_rw	3.32	0.0	2	2	100.00
		lc_ctrl_jtag_csr_bit_bash	21.54	0.0	2	2	100.00
		lc_ctrl_jtag_csr_aliasing	7.53	0.0	2	2	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.19	0.0	2	2	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.13	0.0	2	2	100.00
		lc_ctrl_jtag_alert_test	1.58	0.0	2	2	100.00
		lc_ctrl_tl_errors	3.63	0.0	2	2	100.00
		lc_ctrl_tl_intg_err	1.9	0.0	2	2	100.00
		lc_ctrl_csr_hw_reset	1.29	0.0	2	2	100.00
		lc_ctrl_csr_rw	1.0	0.0	2	2	100.00
		lc_ctrl_csr_bit_bash	2.04	0.0	2	2	100.00
		lc_ctrl_csr_aliasing	1.19	0.0	2	2	100.00
		lc_ctrl_same_csr_outstanding	1.34	0.0	2	2	100.00
		lc_ctrl_csr_mem_rw_with_rand_reset	1.06	0.0	2	2	100.00
		lc_ctrl_smoke	1.62	0.0	2	2	100.00
		lc_ctrl_volatile_unlock_smoke	1.28	0.0	2	2	100.00
		lc_ctrl_state_failure	5.9	0.0	0	2	0.00
		lc_ctrl_state_post_trans	6.48	0.0	2	2	100.00
		lc_ctrl_prog_failure	3.63	0.0	2	2	100.00
		lc_ctrl_errors	8.98	0.0	2	2	100.00
		lc_ctrl_security_escalation	7.97	0.0	2	2	100.00
		lc_ctrl_regwen_during_op	7.62	0.0	2	2	100.00
		lc_ctrl_claim_transition_if	1.07	0.0	2	2	100.00
		lc_ctrl_jtag_smoke	5.38	0.0	2	2	100.00
		lc_ctrl_jtag_state_failure	8.98	0.0	0	2	0.00
		lc_ctrl_jtag_state_post_trans	14.98	0.0	2	2	100.00
		lc_ctrl_jtag_prog_failure	7.28	0.0	2	2	100.00
		lc_ctrl_jtag_errors	18.44	0.0	2	2	100.00
		lc_ctrl_jtag_access	3.95	0.0	2	2	100.00
		lc_ctrl_jtag_priority	3.86	0.0	2	2	100.00
		lc_ctrl_jtag_regwen_during_op	14.26	0.0	2	2	100.00
		lc_ctrl_sec_mubi	11.52	0.0	2	2	100.00
		lc_ctrl_sec_token_mux	7.49	0.0	2	2	100.00
		lc_ctrl_sec_token_digest	7.55	0.0	2	2	100.00
		lc_ctrl_stress_all	58.67	0.0	0	2	0.00
		lc_ctrl_stress_all_with_rand_reset	1.89	0.0	0	2	0.00
		lc_ctrl_sec_cm	8.97	0.0	2	2	100.00
		lc_ctrl_alert_test	1.34	0.0	2	2	100.00
		rom_ctrl_smoke	6.76	0.0	2	2	100.00
		rom_ctrl_stress_all	30.62	0.0	2	2	100.00
		rom_ctrl_max_throughput_chk	8.85	0.0	2	2	100.00
		rom_ctrl_corrupt_sig_fatal_chk	123.71999999999998	0.0	2	2	100.00
		rom_ctrl_kmac_err_chk	15.71	0.0	2	2	100.00
		rom_ctrl_stress_all_with_rand_reset	154.51	0.0	2	2	100.00
		rom_ctrl_sec_cm	243.06	0.0	0	2	0.00
		rom_ctrl_alert_test	7.34	0.0	2	2	100.00
		rom_ctrl_passthru_mem_tl_intg_err	48.29	0.0	2	2	100.00
		rom_ctrl_tl_errors	10.11	0.0	2	2	100.00
		rom_ctrl_tl_intg_err	50.47	0.0	2	2	100.00
		rom_ctrl_mem_walk	8.93	0.0	2	2	100.00
		rom_ctrl_mem_partial_access	8.81	0.0	2	2	100.00
		rom_ctrl_csr_hw_reset	12.62	0.0	2	2	100.00
		rom_ctrl_csr_rw	8.29	0.0	2	2	100.00
		rom_ctrl_csr_bit_bash	9.07	0.0	2	2	100.00
		rom_ctrl_csr_aliasing	5.89	0.0	2	2	100.00
		rom_ctrl_same_csr_outstanding	9.19	0.0	2	2	100.00
		rom_ctrl_csr_mem_rw_with_rand_reset	9.87	0.0	2	2	100.00
		otp_ctrl_tl_errors	3.69	0.0	1	1	100.00
		otp_ctrl_tl_intg_err	19.16	0.0	1	1	100.00
		otp_ctrl_intr_test	1.99	0.0	1	1	100.00
		otp_ctrl_mem_walk	1.64	0.0	1	1	100.00
		otp_ctrl_mem_partial_access	2.09	0.0	1	1	100.00
		otp_ctrl_csr_hw_reset	2.54	0.0	1	1	100.00
		otp_ctrl_csr_rw	2.09	0.0	1	1	100.00
		otp_ctrl_csr_bit_bash	4.78	0.0	1	1	100.00
		otp_ctrl_csr_aliasing	6.22	0.0	1	1	100.00
		otp_ctrl_same_csr_outstanding	3.23	0.0	1	1	100.00
		otp_ctrl_csr_mem_rw_with_rand_reset	2.53	0.0	1	1	100.00
		otp_ctrl_wake_up	1.78	0.0	1	1	100.00
		otp_ctrl_smoke	5.9	0.0	1	1	100.00
		otp_ctrl_partition_walk	133.85	0.0	0	1	0.00
		otp_ctrl_low_freq_read	80.23	0.0	0	1	0.00
		otp_ctrl_init_fail	3.29	0.0	1	1	100.00
		otp_ctrl_background_chks	10.41	0.0	1	1	100.00
		otp_ctrl_parallel_lc_req	5.43	0.0	1	1	100.00
		otp_ctrl_parallel_lc_esc	14.74	0.0	1	1	100.00
		otp_ctrl_dai_lock	7.08	0.0	0	1	0.00
		otp_ctrl_dai_errs	14.89	0.0	1	1	100.00
		otp_ctrl_check_fail	16.94	0.0	0	1	0.00
		otp_ctrl_macro_errs	23.97	0.0	1	1	100.00
		otp_ctrl_parallel_key_req	8.19	0.0	0	1	0.00
		otp_ctrl_regwen	6.25	0.0	1	1	100.00
		otp_ctrl_test_access	4.04	0.0	0	1	0.00
		otp_ctrl_stress_all_with_rand_reset	2.4	0.0	0	1	0.00
		otp_ctrl_stress_all	26.32	0.0	0	1	0.00
		otp_ctrl_sec_cm	138.48	0.0	0	1	0.00
		otp_ctrl_alert_test	2.64	0.0	1	1	100.00
		entropy_src_tl_errors	2.0	37.862489000000004	1	1	100.00
		entropy_src_tl_intg_err	3.0	318.210676	1	1	100.00
		entropy_src_intr_test	2.0	16.278347	1	1	100.00
		entropy_src_csr_hw_reset	2.0	56.263253	1	1	100.00
		entropy_src_csr_rw	2.0	77.942017	1	1	100.00
		entropy_src_csr_bit_bash	13.0	2546.518356	1	1	100.00
		entropy_src_csr_aliasing	4.0	286.766219	1	1	100.00
		entropy_src_same_csr_outstanding	4.0	78.746349	1	1	100.00
		entropy_src_csr_mem_rw_with_rand_reset	2.0	31.140448	1	1	100.00
		entropy_src_smoke	3.0	351.276363	1	1	100.00
		entropy_src_rng	94.0	15251.329271	1	1	100.00
		entropy_src_rng_max_rate	77.0	10287.346952	1	1	100.00
		entropy_src_rng_with_xht_rsps	58.0	12404.867867	1	1	100.00
		entropy_src_stress_all	471.0	19116.171498	1	1	100.00
		entropy_src_fw_ov	312.0	13059.281387	1	1	100.00
		entropy_src_fw_ov_contiguous	4.0	204.409191	1	1	100.00
		entropy_src_intr	3.0	49.304999	1	1	100.00
		entropy_src_functional_alerts	6.0	353.671145	1	1	100.00
		entropy_src_cfg_regwen	2.0	20.396732	1	1	100.00
		entropy_src_functional_errors	3.0	37.78118	1	1	100.00
		entropy_src_sec_cm	3.0	230.509755	1	1	100.00
		entropy_src_alert_test	3.0	22.902621	1	1	100.00
		otbn_smoke	13.0	617.6223560000001	0	1	0.00
		otbn_single	6.0	18.15148	0	1	0.00
		otbn_multi	50.0	857.213873	0	1	0.00
		otbn_reset	24.0	110.971261	0	1	0.00
		otbn_multi_err	40.0	1953.632423	0	1	0.00
		otbn_imem_err	6.0	24.065154	0	1	0.00
		otbn_dmem_err	6.0	43.714433	0	1	0.00
		otbn_escalate	6.0	23.793836	1	1	100.00
		otbn_alu_bignum_mod_err	7.0	27.359560000000002	0	1	0.00
		otbn_controller_ispr_rdata_err	6.0	52.745137	0	1	0.00
		otbn_mac_bignum_acc_err	8.0	227.430248	0	1	0.00
		otbn_rf_bignum_intg_err	9.0	242.637056	0	1	0.00
		otbn_rf_base_intg_err	5.0	36.071375999999994	0	1	0.00
		otbn_stress_all	121.0	447.378207	0	1	0.00
		otbn_stress_all_with_rand_reset	23.0	120.799479	0	1	0.00
		otbn_zero_state_err_urnd	6.0	31.815879000000002	0	1	0.00
		otbn_illegal_mem_acc	4.0	27.554094	1	1	100.00
		otbn_sw_errs_fatal_chk	12.0	95.13936100000001	0	1	0.00
		otbn_pc_ctrl_flow_redun	6.0	69.444699	1	1	100.00
		otbn_rnd_sec_cm	77.0	1969.659966	0	1	0.00
		otbn_ctrl_redun	8.0	25.139361	0	1	0.00
		otbn_sec_wipe_err	6.0	18.867434	0	1	0.00
		otbn_urnd_err	4.0	95.479416	0	1	0.00
		otbn_sw_no_acc	6.0	78.335484	0	1	0.00
		otbn_mem_gnt_acc_err	4.0	33.413177000000005	1	1	100.00
		otbn_stack_addr_integ_chk	6.0	45.188213000000005	0	1	0.00
		otbn_partial_wipe	5.0	88.588067	1	1	100.00
		otbn_sec_cm	5.0	57.691496	0	1	0.00
		otbn_alert_test	4.0	60.019543	1	1	100.00
		otbn_passthru_mem_tl_intg_err	20.0	363.60679200000004	1	1	100.00
		otbn_tl_errors	3.0	154.20369399999998	1	1	100.00
		otbn_tl_intg_err	10.0	146.739384	1	1	100.00
		otbn_intr_test	3.0	19.145138	1	1	100.00
		otbn_mem_walk	28.0	1595.6841689999999	1	1	100.00
		otbn_mem_partial_access	10.0	1203.966367	1	1	100.00
		otbn_csr_hw_reset	3.0	37.675934	1	1	100.00
		otbn_csr_rw	4.0	16.133055	1	1	100.00
		otbn_csr_bit_bash	5.0	176.134256	1	1	100.00
		otbn_csr_aliasing	4.0	18.619040000000002	1	1	100.00
		otbn_same_csr_outstanding	4.0	20.901752000000002	1	1	100.00
		otbn_csr_mem_rw_with_rand_reset	5.0	34.611698	1	1	100.00
		chip_tl_errors	114.46	0.0	0	1	0.00
		chip_prim_tl_access	308.18	0.0	1	1	100.00
		chip_rv_dm_lc_disabled	87.98	0.0	0	1	0.00
		chip_csr_bit_bash	10.87	0.0	0	1	0.00
		chip_csr_aliasing	9.59	0.0	0	1	0.00
		chip_same_csr_outstanding	12.21	0.0	0	1	0.00
		chip_sw_example_rom	29.09	0.0	0	1	0.00
		chip_sw_example_manufacturer	139.51308	0.0	0	1	0.00
		chip_sw_example_concurrency	176.04	0.0	1	1	100.00
		chip_sw_all_escalation_resets	846.5	0.0	0	1	0.00
		chip_sw_rstmgr_rst_cnsty_escalation	903.14	0.0	0	1	0.00
		chip_sw_data_integrity_escalation	119.405766	0.0	0	1	0.00
		chip_sw_sleep_pin_wake	114.985977	0.0	0	1	0.00
		chip_sw_sleep_pin_retention	110.498895	0.0	0	1	0.00
		chip_sw_uart_tx_rx	94.41935	0.0	0	1	0.00
		chip_sw_uart_tx_rx_bootstrap	96.779347	0.0	0	1	0.00
		chip_sw_inject_scramble_seed	87.651044	0.0	0	1	0.00
		chip_sw_exit_test_unlocked_bootstrap	77.235842	0.0	0	1	0.00
		chip_sw_uart_rand_baudrate	55.30707	0.0	0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq	36.24062	0.0	0	1	0.00
		chip_sw_i2c_host_tx_rx	46.187482	0.0	0	1	0.00
		chip_sw_i2c_device_tx_rx	23.132199	0.0	0	1	0.00
		chip_sw_spi_device_tpm	10.638888	0.0	0	1	0.00
		chip_sw_spi_host_tx_rx	21.887915	0.0	0	1	0.00
		chip_sw_spi_device_pass_through	2329.83	0.0	1	1	100.00
		chip_sw_spi_device_pass_through_collision	269.26	0.0	0	1	0.00
		chip_sw_gpio	276.74	0.0	1	1	100.00
		chip_sw_kmac_entropy	224.5	0.0	1	1	100.00
		chip_sw_lc_ctrl_otp_hw_cfg	10.739797	0.0	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.163448	0.0	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	10.020296	0.0	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.020656	0.0	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.042469	0.0	0	1	0.00
		chip_sw_otp_ctrl_vendor_test_csr_access	16.042329	0.0	0	1	0.00
		chip_sw_otp_ctrl_escalation	188.64	0.0	0	1	0.00
		chip_sw_otp_ctrl_nvm_cnt	15.964079	0.0	0	1	0.00
		chip_sw_otp_ctrl_sw_parts	12.545337	0.0	0	1	0.00
		chip_sw_lc_ctrl_transition	9.577531	0.0	0	1	0.00
		chip_sw_lc_ctrl_rma_to_scrap	190.7	0.0	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	200.73	0.0	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	174.37	0.0	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	178.5	0.0	1	1	100.00
		chip_sw_lc_walkthrough_dev	18.866154	0.0	0	1	0.00
		chip_sw_lc_walkthrough_prod	19.697927	0.0	0	1	0.00
		chip_sw_lc_walkthrough_prodend	19.341935	0.0	0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock	523.37	0.0	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	429.18	0.0	1	1	100.00
		chip_sw_lc_walkthrough_rma	16.252871	0.0	0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.881724	0.0	0	1	0.00
		chip_sw_rstmgr_sw_req	272.88	0.0	1	1	100.00
		chip_sw_rstmgr_sw_rst	159.8	0.0	1	1	100.00
		chip_sw_rstmgr_alert_info	287.54	0.0	0	1	0.00
		chip_sw_rstmgr_cpu_info	352.38	0.0	0	1	0.00
		chip_sw_pwrmgr_full_aon_reset	342.42	0.0	1	1	100.00
		chip_sw_pwrmgr_main_power_glitch_reset	15.447437	0.0	0	1	0.00
		chip_sw_pwrmgr_sleep_power_glitch_reset	10.294711	0.0	0	1	0.00
		chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.914896	0.0	0	1	0.00
		chip_sw_pwrmgr_random_sleep_power_glitch_reset	16.013684	0.0	0	1	0.00
		chip_sw_pwrmgr_sleep_disabled	9.842049	0.0	0	1	0.00
		chip_sw_rv_timer_irq	249.70999999999998	0.0	1	1	100.00
		chip_sw_soc_proxy_smoketest	150.37	0.0	0	1	0.00
		chip_sw_soc_proxy_external_wakeup	148.92	0.0	0	1	0.00
		chip_sw_soc_proxy_gpios	158.45	0.0	0	1	0.00
		chip_sw_aon_timer_irq	453.15	0.0	0	1	0.00
		chip_sw_aon_timer_sleep_wdog_sleep_pause	298.7	0.0	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	195.95	0.0	0	1	0.00
		chip_sw_pwrmgr_wdog_reset	9.614662	0.0	0	1	0.00
		chip_sw_aon_timer_wdog_lc_escalate	11.405322	0.0	0	1	0.00
		chip_sw_otbn_randomness	273.35	0.0	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq	2201.51	0.0	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	37.76	0.0	0	1	0.00
		chip_sw_otbn_mem_scramble	356.37	0.0	1	1	100.00
		chip_sw_rv_core_ibex_rnd	188.64	0.0	1	1	100.00
		chip_sw_rv_core_ibex_nmi_irq	331.64	0.0	0	1	0.00
		chip_sw_aes_enc	178.74	0.0	1	1	100.00
		chip_sw_aes_enc_jitter_en	38.75	0.0	0	1	0.00
		chip_sw_aes_idle	157.41	0.0	1	1	100.00
		chip_sw_aes_masking_off	183.47	0.0	1	1	100.00
		chip_sw_alert_test	17.402343	0.0	0	1	0.00
		chip_sw_alert_handler_escalation	9.651373	0.0	0	1	0.00
		chip_sw_alert_handler_ping_timeout	14.353393	0.0	0	1	0.00
		chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.490576	0.0	0	1	0.00
		chip_sw_alert_handler_lpg_sleep_mode_alerts	13.578243	0.0	0	1	0.00
		chip_sw_alert_handler_lpg_sleep_mode_pings	11.340255	0.0	0	1	0.00
		chip_sw_alert_handler_lpg_clkoff	10.052919	0.0	0	1	0.00
		chip_sw_alert_handler_lpg_reset_toggle	9.818431	0.0	0	1	0.00
		chip_sw_alert_handler_entropy	10.656118	0.0	0	1	0.00
		chip_sw_aes_entropy	168.45	0.0	1	1	100.00
		chip_sw_csrng_edn_concurrency	12.060251	0.0	0	1	0.00
		chip_sw_csrng_kat_test	175.05	0.0	1	1	100.00
		chip_sw_csrng_fuse_en_sw_app_read_test	13.252031	0.0	0	1	0.00
		chip_sw_entropy_src_csrng	371.58	0.0	1	1	100.00
		chip_sw_entropy_src_kat_test	144.79	0.0	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	158.87	0.0	1	1	100.00
		chip_sw_hmac_enc	181.01	0.0	1	1	100.00
		chip_sw_hmac_enc_jitter_en	39.61	0.0	0	1	0.00
		chip_sw_hmac_enc_idle	192.74	0.0	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	267.24	0.0	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_prod	290.57	0.0	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	38.32	0.0	0	1	0.00
		chip_sw_kmac_mode_cshake	159.37	0.0	1	1	100.00
		chip_sw_kmac_mode_kmac	206.28	0.0	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	40.41	0.0	0	1	0.00
		chip_sw_kmac_app_rom	30.58	0.0	0	1	0.00
		chip_sw_kmac_idle	166.41	0.0	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	754.52	0.0	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	329.35	0.0	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.347874	0.0	0	1	0.00
		chip_sw_sram_ctrl_execution_main	9.395419	0.0	0	1	0.00
		chip_sw_coremark	9.981428	0.0	0	1	0.00
		chip_plic_all_irqs_0	401.43	0.0	1	1	100.00
		chip_plic_all_irqs_10	353.49	0.0	1	1	100.00
		chip_sw_plic_sw_irq	167.04	0.0	1	1	100.00
		chip_sw_clkmgr_off_aes_trans	183.3	0.0	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	176.59	0.0	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	167.37	0.0	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	163.38	0.0	0	1	0.00
		chip_sw_clkmgr_reset_frequency	11.956313	0.0	0	1	0.00
		chip_sw_clkmgr_jitter	149.1	0.0	1	1	100.00
		chip_sw_clkmgr_sleep_frequency	12.549735	0.0	0	1	0.00
		chip_jtag_csr_rw	116.53	0.0	0	1	0.00
		chip_jtag_mem_access	115.86	0.0	0	1	0.00
		chip_sw_ast_clk_outputs	10.172103	0.0	0	1	0.00
		chip_sw_lc_ctrl_program_error	10.908404	0.0	0	1	0.00
		chip_rv_dm_ndm_reset_req	237.0	0.0	1	1	100.00
		chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	9.394022	0.0	0	1	0.00
		chip_sw_rv_dm_access_after_wakeup	11.428287	0.0	0	1	0.00
		chip_sw_rv_dm_access_after_escalation_reset	10.876173	0.0	0	1	0.00
		chip_sw_rv_core_ibex_address_translation	172.82	0.0	1	1	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	129.85	0.0	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	153.74	0.0	1	1	100.00
		chip_sw_clkmgr_jitter_reduced_freq	295.03	0.0	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	38.35	0.0	0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	37.19	0.0	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	50.69	0.0	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	36.15	0.0	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	37.03	0.0	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	37.25	0.0	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.064808	0.0	0	1	0.00
		chip_sw_power_virus	11.456042	0.0	0	1	0.00
		chip_sw_dma_inline_hashing	173.3	0.0	1	1	100.00
		chip_sw_dma_abort	154.27	0.0	0	1	0.00
		base_rom_e2e_smoke	11.405406	0.0	0	1	0.00
		rom_e2e_smoke	11.158606	0.0	0	1	0.00
		rom_e2e_shutdown_exception_c	12.079258	0.0	0	1	0.00
		rom_e2e_shutdown_output	10.653198	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.940791	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	9.574399	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	9.451853	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	9.91942	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.886209	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.554996	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.197112	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	9.718672	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.933746	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.276993	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	70.20007	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	71.518957	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	108.994702	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	58.550401	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	130.784389	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	58.022462	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	70.493537	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	57.44017	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	71.616426	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	71.523105	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	64.467637	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	73.98302	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	101.036373	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	79.668027	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	88.714753	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.451569	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.94382	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	19.45829	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	10.162765	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	14.785446	0.0	0	1	0.00
		rom_e2e_asm_init_test_unlocked0	16.614666	0.0	0	1	0.00
		rom_e2e_asm_init_dev	9.953799	0.0	0	1	0.00
		rom_e2e_asm_init_prod	9.34105	0.0	0	1	0.00
		rom_e2e_asm_init_prod_end	9.505791	0.0	0	1	0.00
		rom_e2e_asm_init_rma	10.922111	0.0	0	1	0.00
		rom_e2e_jtag_debug_test_unlocked0	9.791291	0.0	0	1	0.00
		rom_e2e_jtag_debug_dev	13.885433	0.0	0	1	0.00
		rom_e2e_jtag_debug_rma	16.940494	0.0	0	1	0.00
		rom_e2e_jtag_inject_test_unlocked0	9.506677	0.0	0	1	0.00
		rom_e2e_jtag_inject_dev	10.298341	0.0	0	1	0.00
		rom_e2e_jtag_inject_rma	11.753086	0.0	0	1	0.00
		rom_e2e_static_critical	9.552841	0.0	0	1	0.00
		rom_e2e_keymgr_init_rom_ext_meas	14.331543	0.0	0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.272002	0.0	0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	18.37714	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.410047	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	9.854306	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.977272	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.845857	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	9.427998	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	15.89526	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	12.332766	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	9.773043	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	9.551397	0.0	0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	9.110298	0.0	0	1	0.00
		rom_volatile_raw_unlock	47.611972	0.0	0	1	0.00
		rom_raw_unlock	11.118355	0.0	0	1	0.00
		rom_e2e_self_hash	10.029463	0.0	0	1	0.00
		chip_sw_uart_smoketest_signed	10.337637	0.0	0	1	0.00
		rom_keymgr_functest	25.250273	0.0	0	1	0.00
		chip_sw_aes_smoketest	139.87	0.0	1	1	100.00
		chip_sw_aon_timer_smoketest	149.02	0.0	1	1	100.00
		chip_sw_clkmgr_smoketest	122.65000000000002	0.0	1	1	100.00
		chip_sw_csrng_smoketest	133.33	0.0	1	1	100.00
		chip_sw_entropy_src_smoketest	160.86	0.0	1	1	100.00
		chip_sw_gpio_smoketest	144.91	0.0	1	1	100.00
		chip_sw_hmac_smoketest	164.9	0.0	1	1	100.00
		chip_sw_kmac_smoketest	153.26	0.0	1	1	100.00
		chip_sw_mbx_smoketest	267.91	0.0	1	1	100.00
		chip_sw_otbn_smoketest	187.33	0.0	1	1	100.00
		chip_sw_otp_ctrl_smoketest	129.83	0.0	1	1	100.00
		chip_sw_rv_plic_smoketest	125.95999999999998	0.0	1	1	100.00
		chip_sw_rv_timer_smoketest	185.31	0.0	1	1	100.00
		chip_sw_rstmgr_smoketest	125.56	0.0	1	1	100.00
		chip_sw_sram_ctrl_smoketest	130.27	0.0	1	1	100.00
		chip_sw_uart_smoketest	127.3	0.0	1	1	100.00
		chip_padctrl_attributes	2.67	0.0	0	1	0.00
		TOTAL			987	1241	79.53

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.35	97.24	93.54	100.00	57.85	95.33	97.58	90.94

Failure Buckets

• Job returned non-zero exit code has 122 failures:

  • Test chip_sw_example_manufacturer has 1 failures.

    • 0.chip_sw_example_manufacturer.36094243990332956273275204954529506618714122936975113409991001064704639568611
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

        Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 129.201s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test chip_sw_data_integrity_escalation has 1 failures.

    • 0.chip_sw_data_integrity_escalation.113708022949463184679028509589904141167420127446174058906823319806434015657813
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

        Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 110.167s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test chip_sw_sleep_pin_wake has 1 failures.

    • 0.chip_sw_sleep_pin_wake.48363014970164966423665456557854711447512463771881406327890350110039886161575
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 105.765s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test chip_sw_sleep_pin_retention has 1 failures.

    • 0.chip_sw_sleep_pin_retention.74865942900905492726880065844596976552233667481298832862440601628487575134991
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 101.178s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test chip_sw_uart_tx_rx has 1 failures.

    • 0.chip_sw_uart_tx_rx.87757676560914809882892641413089375893901815093072800712734891508885205723611
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

        Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 84.952s, Critical Path: 0.02s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • ... and 117 more tests.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 11 failures:

  • Test chip_sw_otbn_ecdsa_op_irq_jitter_en has 1 failures.

    • 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.22224584545738353824855264727637763654139365312755343605967517368999272122616
      Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log

        UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_aes_enc_jitter_en has 1 failures.

    • 0.chip_sw_aes_enc_jitter_en.34450080042895584930688796104719633280546642273588584725264840625725261830749
      Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_hmac_enc_jitter_en has 1 failures.

    • 0.chip_sw_hmac_enc_jitter_en.93866193149585831697367841315971856974143152338047827093739439544162484122062
      Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.32958836288429533800760771903252495754921386493561109572636640503324393582951
      Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log

        UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.

    • 0.chip_sw_kmac_mode_kmac_jitter_en.90501104620525946342712637674683956252803664910666122862013229197739745432187
      Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log

        UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 6 more tests.

• Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 9 failures:

  • Test lc_ctrl_state_failure has 2 failures.

    • 0.lc_ctrl_state_failure.66910538110246677017931069980751180210111866179600655564165412201279548648483
      Line 1506, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_state_failure/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 316927762 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 316927762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.lc_ctrl_state_failure.50566513704718081017133046397947713947255070049118269825908265156930590076604
      Line 428, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_state_failure/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @  76630361 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @  76630361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_jtag_state_failure has 2 failures.

    • 0.lc_ctrl_jtag_state_failure.94393518515441216984879993564704615093836978326830898750141724464779610924488
      Line 236, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @  61866262 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @  61866262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.lc_ctrl_jtag_state_failure.39091061913530733984244257809115490473419173837830260697078148984203368249932
      Line 823, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 811606320 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 811606320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 2 failures.

    • 0.lc_ctrl_stress_all.28721747958910556320990183075792939027971838806038873231607218038763335638153
      Line 2411, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 3571202396 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 3571202396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.lc_ctrl_stress_all.18641557952979640281607732192020926018802217579606721499299040338048244419486
      Line 5057, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 3054366610 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 3054366610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.2880396527923469070652110052519565004163398733706365174592205962395194755635
      Line 193, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @   4867137 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @   4867137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.lc_ctrl_stress_all_with_rand_reset.37590745483361522981754807168940943424063130491147116768307315347913823229001
      Line 193, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @  69566023 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @  69566023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_otp_ctrl_escalation has 1 failures.

    • 0.chip_sw_otp_ctrl_escalation.4515976829231420835142729846998424141367784583560126752220504868421470969453
      Line 446, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 158.248000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 158.248000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@*_*.mnemonic_cp) is an illegal value. has 9 failures:

  • Test otbn_reset has 1 failures.

    • 0.otbn_reset.18556053774135332787952579352287846045772043571034434921931484956643710666997
      Line 112, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_reset/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 9805725 PS + 23) Sampled value (27767) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1488):(Time: 9805725 PS + 23) Sampled value (27767) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_xw_cg@4234_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 9816251 PS + 23) Sampled value (27767) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 9816251 PS + 23) Sampled value (29559) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1314):(Time: 9816251 PS + 23) Sampled value (29559) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_s_cg@4222_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_multi_err has 1 failures.

    • 0.otbn_multi_err.2187568476109348537832544117480851261742629035328542150193699499443556366665
      Line 205, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 53920032 PS + 26) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 54062889 PS + 20) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 54062889 PS + 20) Sampled value (108225364781412) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1122):(Time: 54062889 PS + 20) Sampled value (108225364781412) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_bnxid_cg@4213_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1956):(Time: 54062889 PS + 20) Sampled value (108225364781412) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_bn_xid_cg@4247_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_imem_err has 1 failures.

    • 0.otbn_imem_err.27248631546025278373440272383562939304909409870158631388934824224074689823913
      Line 115, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_imem_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 7748839 PS + 19) Sampled value (1784769650) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 7786575 PS + 23) Sampled value (1784769650) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 7786575 PS + 23) Sampled value (7892850) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 7786575 PS + 23) Sampled value (7892850) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1462):(Time: 7786575 PS + 23) Sampled value (7892850) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_log_binop_cg@4233_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_dmem_err has 1 failures.

    • 0.otbn_dmem_err.26980689916394904242934170789402170943925925692779539540164085714274908935158
      Line 107, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 12872390 PS + 27) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 12912390 PS + 23) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 12912390 PS + 23) Sampled value (427138642551) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 12912390 PS + 23) Sampled value (427138642551) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 12952390 PS + 21) Sampled value (427138642551) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

  • Test otbn_alu_bignum_mod_err has 1 failures.

    • 0.otbn_alu_bignum_mod_err.79940452239986135177880481715640335607441685917056350372897106506421809491161
      Line 107, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 10659560 PS + 23) Sampled value (2020569705) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1462):(Time: 10659560 PS + 23) Sampled value (2020569705) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_log_binop_cg@4233_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 10679560 PS + 23) Sampled value (2020569705) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 10679560 PS + 23) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1223):(Time: 10679560 PS + 23) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@4217_1.mnemonic_cp) is an illegal value.
      

  • ... and 4 more tests.

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@*_*.mnemonic_cp) is an illegal value. has 7 failures:

  • Test otbn_mac_bignum_acc_err has 1 failures.

    • 0.otbn_mac_bignum_acc_err.106674590381362503946510001710439236548801695585288969534503864584928890519010
      Line 103, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 17054636 PS + 26) Sampled value (7892850) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1462):(Time: 17054636 PS + 26) Sampled value (7892850) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_log_binop_cg@4233_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 17094636 PS + 29) Sampled value (7892850) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 17094636 PS + 29) Sampled value (27705693569249906) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1344):(Time: 17094636 PS + 29) Sampled value (27705693569249906) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_wcsr_cg@4223_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_rf_bignum_intg_err has 1 failures.

    • 0.otbn_rf_bignum_intg_err.77230747274560424705393437325210398316699550419388349076207544866768725055681
      Line 117, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_bignum_intg_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 15134343 PS + 20) Sampled value (7564396) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 15179798 PS + 20) Sampled value (7564396) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 15179798 PS + 20) Sampled value (28530) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 15179798 PS + 20) Sampled value (28530) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1462):(Time: 15179798 PS + 20) Sampled value (28530) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_log_binop_cg@4233_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_rf_base_intg_err has 1 failures.

    • 0.otbn_rf_base_intg_err.60989492017022508566078188107552452241041528508112546720116936692359400426310
      Line 110, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 14476276 PS + 12) Sampled value (7565921) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        UVM_INFO @  36071376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otbn_stress_all has 1 failures.

    • 0.otbn_stress_all.57112518862589863702759155183539788092553738234449463371617940859652847029728
      Line 144, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 25111123 PS + 21) Sampled value (7565921) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4222_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 25121432 PS + 20) Sampled value (7565921) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 25121432 PS + 20) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 25121432 PS + 20) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4217_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 25131741 PS + 21) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.last_cp) is an illegal value.
      

  • Test otbn_sw_errs_fatal_chk has 1 failures.

    • 0.otbn_sw_errs_fatal_chk.53373842716165054191485763951919069421119686571257223805477062808346986939764
      Line 106, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 15606626 PS + 20) Sampled value (7566690) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1363):(Time: 15606626 PS + 20) Sampled value (7566690) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_addsub_cg@4225_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 15626626 PS + 25) Sampled value (7566690) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 15626626 PS + 25) Sampled value (7565932) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 15626626 PS + 25) Sampled value (7565932) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
      

  • ... and 2 more tests.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:

  • Test rv_dm_sba_tl_access has 1 failures.

    • 0.rv_dm_sba_tl_access.111283560344574916029139928040418413071137905136533970387599376592378616533319
      Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_delayed_resp_sba_tl_access has 1 failures.

    • 0.rv_dm_delayed_resp_sba_tl_access.18239596914755255280617895499166212806009312377115750245234468619920177749181
      Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_bad_sba_tl_access has 1 failures.

    • 0.rv_dm_bad_sba_tl_access.46791879223375757069450733630540014543685317887866872080629989557038369770115
      Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_autoincr_sba_tl_access has 1 failures.

    • 0.rv_dm_autoincr_sba_tl_access.83434711820489585800118710361269941746280425581111467831881154925874105938227
      Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_scanmode has 1 failures.

    • 0.rv_dm_scanmode.30451791431760186481791679243672927301230876090400931795860685588536931883921
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_scanmode/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 1 more tests.

• Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 6 failures:

  • Test chip_sw_rstmgr_cpu_info has 1 failures.

    • 0.chip_sw_rstmgr_cpu_info.26863088803067309084379065019479696144843783722412500099789250768446434776028
      Line 447, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 375.152000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 375.152000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_soc_proxy_smoketest has 1 failures.

    • 0.chip_sw_soc_proxy_smoketest.98017561087240589657976628734442215621994362562259440242848057756542798336382
      Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log

            Offending '((!rstreqs[1]) && (reset_cause != HwReq))'
        UVM_ERROR @ 143.536000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 143.536000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_clkmgr_off_aes_trans has 1 failures.

    • 0.chip_sw_clkmgr_off_aes_trans.40188352000834562583685003049162798865339964265999180884781506402536683793305
      Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

    • 0.chip_sw_clkmgr_off_hmac_trans.89189153819504651302707716352210010008208932693272875243981546941723038546502
      Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.632000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.632000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

    • 0.chip_sw_clkmgr_off_kmac_trans.106675736876922291938154911035501999950539863284277845420202234693093607779671
      Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.680000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.680000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 1 more tests.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * has 4 failures:

  • Test clkmgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.clkmgr_shadow_reg_errors_with_csr_rw.19303019113010730216470683834427669009517076334385017057238829582535957184342
      Line 72, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  24384750 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
        UVM_INFO @  24384750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test clkmgr_tl_intg_err has 1 failures.

    • 0.clkmgr_tl_intg_err.11242275836258638892768974090834836858385162021435191878627833190026659719395
      Line 82, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest/run.log

        UVM_ERROR @   3244197 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
        UVM_INFO @   3244197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test clkmgr_csr_aliasing has 1 failures.

    • 0.clkmgr_csr_aliasing.78485617418084752418603987637823658053285743179497795698773945586043881471742
      Line 73, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest/run.log

        UVM_ERROR @  19351646 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
        UVM_INFO @  19351646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test clkmgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.clkmgr_csr_mem_rw_with_rand_reset.35418454058552066369439540434668277998908379708820842107499682497779080876055
      Line 73, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  26371411 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
        UVM_INFO @  26371411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* has 3 failures:

  • Test clkmgr_frequency_timeout has 1 failures.

    • 0.clkmgr_frequency_timeout.101783071661752253366023081810149571360526954552103316107201048898930581335403
      Line 74, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log

        UVM_ERROR @   7754169 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
        UVM_INFO @   7754169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 0.clkmgr_stress_all_with_rand_reset.88531580588710139699305269058417874749565941897298644493777405280766094773313
      Line 76, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  21458796 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
        UVM_INFO @  21458796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test clkmgr_stress_all has 1 failures.

    • 0.clkmgr_stress_all.30800508599262512093949882506902215190870161346730810949279465668991337337238
      Line 122, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all/latest/run.log

        UVM_ERROR @  31785126 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
        UVM_INFO @  31785126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@*_*.mnemonic_cp) is an illegal value. has 3 failures:

  • Test otbn_single has 1 failures.

    • 0.otbn_single.65662885821580070491480169600545485195773653722769748357088850969078952371478
      Line 116, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_single/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1223):(Time: 10067362 PS + 23) Sampled value (1936485481) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@4217_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 10077888 PS + 25) Sampled value (1936485481) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 10077888 PS + 25) Sampled value (6382692) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 10077888 PS + 25) Sampled value (6382692) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1363):(Time: 10077888 PS + 25) Sampled value (6382692) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_addsub_cg@4225_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_multi has 1 failures.

    • 0.otbn_multi.41680790772594926648675206986638683184923421964560897966958373454781908603143
      Line 149, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1223):(Time: 19290543 PS + 20) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@4217_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 19332210 PS + 21) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 19332210 PS + 21) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1223):(Time: 19332210 PS + 21) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@4217_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 19373877 PS + 27) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

  • Test otbn_sw_no_acc has 1 failures.

    • 0.otbn_sw_no_acc.12068488748994784222324259825852599204174284874434316403495862512636690767063
      Line 111, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sw_no_acc/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1223):(Time: 25272984 PS + 20) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@4217_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 25335484 PS + 20) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 25335484 PS + 20) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1223):(Time: 25335484 PS + 20) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@4217_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 25397984 PS + 21) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:

  • Test chip_csr_bit_bash has 1 failures.

    • 0.chip_csr_bit_bash.25278532827968376450666440676327306483352615212185975430995114260707213873387
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_csr_aliasing has 1 failures.

    • 0.chip_csr_aliasing.45530671848626844204107519759713603094229969902686272364430559556490181060475
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_same_csr_outstanding has 1 failures.

    • 0.chip_same_csr_outstanding.82932782703483814308503565880725181720559587327000319435433554030684336853872
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[NOA] Null object access has 2 failures:

  • Test rv_dm_tap_fsm has 1 failures.

    • 0.rv_dm_tap_fsm.32754497038850901641202934458625940815330309660107008840333977872101992691284
      Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log

        Error-[NOA] Null object access
        src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, 652
          The object at dereference depth 0 is being used before it was
          constructed/allocated.
          Please make sure that the object is allocated before using it.
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.58631356469114083609170081366963234615410410976088309823922417933187077085152
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        Error-[NOA] Null object access
        src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
          The object at dereference depth 0 is being used before it was
          constructed/allocated.
          Please make sure that the object is allocated before using it.
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.36910761808235626011838158440831949312822666091298387173578548157484693202349
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 11678970ps failed at 11678970ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv", 211: tb.dut.u_tlul_adapter_sram_racl.tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth: started at 11699804ps failed at 11699804ps
            Offending '(depth_o <= 2'(Depth))'
      

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.67416241740001938878260314247455079471535666986384568955700116597997949021540
      Line 105, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 14697389ps failed at 14697389ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 14697389ps failed at 14697389ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.113381254840596675248329714504790253163103215832233538663547007419934165175581
      Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 597685050 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 597685050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.114956402361346153060446003749844832038497461676780776645446368505329108673513
      Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5267970732 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5267970732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == gmv(ral.loc_alert_cause[i]) (* [] vs * [])` has 2 failures:

  • Test alert_handler_ping_timeout has 1 failures.

    • 0.alert_handler_ping_timeout.31214634218744153916033036061293164944121344687271382760607560762562019115384
      Line 77, in log /nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 397408158 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 397408158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test alert_handler_lpg has 1 failures.

    • 0.alert_handler_lpg.72831446823374612036792577712316737355063956850510612791491781375475037498520
      Line 77, in log /nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_lpg/latest/run.log

        UVM_ERROR @ 1498677583 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 1498677583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 2 failures:

  • Test otp_ctrl_dai_lock has 1 failures.

    • 0.otp_ctrl_dai_lock.10880234510660248693512578591875118996891906497712254801413227506900332015543
      Line 4902, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest/run.log

        UVM_ERROR @ 1196682036 ps: (otp_ctrl_scoreboard.sv:1250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 1196682036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otp_ctrl_stress_all has 1 failures.

    • 0.otp_ctrl_stress_all.99814749338636840026157445108471053680782682327875979457907349170388634595725
      Line 26814, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 4544830175 ps: (otp_ctrl_scoreboard.sv:1250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 4544830175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* has 2 failures:

  • Test otp_ctrl_parallel_key_req has 1 failures.

    • 0.otp_ctrl_parallel_key_req.94562828629217477398643802003582229311818702904392604717067177708089802560640
      Line 6867, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest/run.log

        UVM_ERROR @ 1881880694 ps: (otp_ctrl_scoreboard.sv:1250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
        UVM_INFO @ 1881880694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otp_ctrl_test_access has 1 failures.

    • 0.otp_ctrl_test_access.27587364968847669923883359959470492801207284787915379702395303038253366276381
      Line 3187, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest/run.log

        UVM_ERROR @ 332397677 ps: (otp_ctrl_scoreboard.sv:1250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
        UVM_INFO @ 332397677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 2 failures:

  • Test chip_sw_all_escalation_resets has 1 failures.

    • 0.chip_sw_all_escalation_resets.20843923684979013922398902274929640464851191971037378057423040707006885215500
      Line 457, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 905.622000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
        UVM_INFO @ 905.622000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.

    • 0.chip_sw_rstmgr_rst_cnsty_escalation.17695890259392961161793653307336421447724493405309661921679645082616139135577
      Line 463, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

        UVM_ERROR @ 905.718000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
        UVM_INFO @ 905.718000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

  • Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation.48717091732492976302069664454569343287451371713298274043865982140990531588194
      Line 444, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

        UVM_ERROR @ 268.007000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (7475998109885483743982608345446346064764672827307591448548872178021973854348226007259118368245529473909092425361224851919531092592289001912333985294670940 [0x8ebdeae5aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd308eb5a147f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 268.007000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation_prod.37302117466385108431694547149056400434077874846791215573126665718639980154152
      Line 452, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

        UVM_ERROR @ 268.299000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (4988495253119922808358709232791021344666179344019638341054395099052729366834399077573842855902690487012290622117896745172549425333683311548313655333706844 [0x5f3f41c2aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3d969f1337f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 268.299000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42094) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

  • Test chip_jtag_csr_rw has 1 failures.

    • 0.chip_jtag_csr_rw.91283459115535956415339098088695589347109368943343715172974673645312028388223
      Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

        UVM_ERROR @ 117.024000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42094) { a_addr: 'h30480000  a_data: 'h7de5c198  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h1  a_user: 'h2488f  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 117.024000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_jtag_mem_access has 1 failures.

    • 0.chip_jtag_mem_access.39720792460891033851708939744377338321976453288667603645796672600509439147810
      Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

        UVM_ERROR @ 117.037000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42094) { a_addr: 'h30480000  a_data: 'hd1b7f992  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6  a_opcode: 'h1  a_user: 'h24885  d_param: 'h0  d_source: 'h6  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 117.037000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs * [])` has 1 failures:

  • Test rv_dm_mem_tl_access_resuming has 1 failures.

    • 0.rv_dm_mem_tl_access_resuming.12726939680771239839869061583101556411783337336895064979066927648762551248517
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log

        UVM_ERROR @  97225190 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @  97225190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 1 failures:

  • Test rv_dm_hart_unavail has 1 failures.

    • 0.rv_dm_hart_unavail.27945021110636501275600883379001852376686535847879821271708439066256775954952
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest/run.log

        UVM_ERROR @ 265548773 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 265548773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:

  • Test rv_dm_jtag_dmi_debug_disabled has 1 failures.

    • 0.rv_dm_jtag_dmi_debug_disabled.90838642500674402387302919634310511541898987602535560497197546008815011629290
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log

        UVM_ERROR @ 480275286 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (774790258 [0x2e2e5c72] vs 0 [0x0])
        UVM_INFO @ 480275286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5800) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test rv_dm_stress_all_with_rand_reset has 1 failures.

    • 0.rv_dm_stress_all_with_rand_reset.34375242257987627041947925068217528448558063643746464750336182850615743129803
      Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  49477104 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5800) { a_addr: 'h201cf738  a_data: 'h594592d1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf4  a_opcode: 'h4  a_user: 'h195fa  d_param: 'h0  d_source: 'hf4  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @  49477104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.46853318012442449503843374733789443828187180943757210635385000568135748830486
      Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 4653380111 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 4653421778 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 4653463445 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (186 [0xba] vs 223 [0xdf]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 4812839720 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 4812839720 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.104677110465238297244981149896422821572507901995156600342943892646268687795349
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 177158770 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 177158770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 1 failures:

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.46099145266852857741093519615588854625911800667156218077193822507401561480196
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @  69096431 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x76bf3d04) == 0x1
        UVM_INFO @  69096431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.7632398149795893738166528350729661769901039061262922336104908944453185086188
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1903629 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[67])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1903629 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1903629 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[963])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.1518016348265865406379410212262311183347385268126501538907730117429667789914
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    909611 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe797f6 [111001111001011111110110] vs 0x0 [0])
        UVM_ERROR @   1006611 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4ca9f5 [10011001010100111110101] vs 0x0 [0])
        UVM_ERROR @   1063611 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x280521 [1010000000010100100001] vs 0x0 [0])
        UVM_ERROR @   1094611 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbb7481 [101110110111010010000001] vs 0x0 [0])
        UVM_ERROR @   1165611 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x968133 [100101101000000100110011] vs 0x0 [0])
      

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.41266716758108760505596746736792002040645870838321766679624143081040515780879
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2991957622 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1a) != exp (0x7e)
        UVM_INFO @ 2991957622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.60986097424191599143801582368945088457250167968149257092625339871056982685071
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  12844216 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  12844216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6144) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test rv_dm_tap_fsm_rand_reset has 1 failures.

    • 0.rv_dm_tap_fsm_rand_reset.76621947155179647722609714375514943724462175212591862756379850857746049653954
      Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log

        UVM_ERROR @  21706006 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6144) { a_addr: 'hd8c6c424  a_data: 'h2952237d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h42  a_opcode: 'h4  a_user: 'h1b855  d_param: 'h0  d_source: 'h42  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @  21706006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5424) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test rv_dm_tl_errors has 1 failures.

    • 0.rv_dm_tl_errors.98319210892049750422271471729600890483837238182976957345964109828062602532029
      Line 75, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log

        UVM_ERROR @  20054046 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5424) { a_addr: 'h6b8b5408  a_data: 'hd883d9c1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h96  a_opcode: 'h4  a_user: 'h1846a  d_param: 'h0  d_source: 'h96  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @  20054046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5611) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test rv_dm_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.rv_dm_csr_mem_rw_with_rand_reset.33303887847042898689350407248421992944754333541115214891725051516694968114026
      Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  42848279 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5611) { a_addr: 'h9eee9574  a_data: 'h1d209ca3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h52  a_opcode: 'h4  a_user: 'h1a885  d_param: 'h0  d_source: 'h52  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @  42848279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 1 failures:

  • Test clkmgr_frequency has 1 failures.

    • 0.clkmgr_frequency.69127823235666786366648919374349000275480006550946278278399794968982838547109
      Line 72, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log

        UVM_ERROR @   8227916 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00
        UVM_INFO @   8227916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed has 1 failures:

  • Test clkmgr_regwen has 1 failures.

    • 0.clkmgr_regwen.12410493528347448664405439487735641466603969176883941794278088027484277058820
      Line 71, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_regwen/latest/run.log

        UVM_ERROR @   7089091 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed
        UVM_INFO @   7089091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * has 1 failures:

  • Test clkmgr_csr_bit_bash has 1 failures.

    • 0.clkmgr_csr_bit_bash.66817220650723448513387839068849968341945087368214105204801064737682929171905
      Line 72, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest/run.log

        UVM_ERROR @   2447017 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0
        UVM_INFO @   2447017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:642) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:

  • Test clkmgr_same_csr_outstanding has 1 failures.

    • 0.clkmgr_same_csr_outstanding.3279094279089102561493180387981725126966455831537501461542751324514300477115
      Line 72, in log /nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest/run.log

        UVM_ERROR @   7860316 ps: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x699ad4a4 read out mismatch
        UVM_INFO @   7860316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.22181817458990867939627852092320404636453654594572247497979644628874797355686
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  86402617 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  86402617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.114058655667291234740066225479634097967514814370377336535037714663450914757674
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 3386465888 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 3386465888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.91837764914860318063844126847566630035059559681449702483327539682033029747649
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 153178574 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 178 [0xb2])
        UVM_INFO @ 153178574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.95709643250771838889148953806744532177621888405241970478641225842223303656603
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 295508036 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 295508036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 0.alert_handler_stress_all_with_rand_reset.89119335543547505608248126643752927101764061573015824151142859390505569605722
      Line 269, in log /nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7670401820 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7670401820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:

  • Test mbx_imbx_oob has 1 failures.

    • 0.mbx_imbx_oob.53504304172881690773896012468530882214828045605102662544194637371129545788758
      Line 95, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log

        UVM_ERROR @ 190411537 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 190411537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (ac_range_check_scoreboard.sv:362) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state has 1 failures:

  • Test ac_range_check_stress_all has 1 failures.

    • 0.ac_range_check_stress_all.58478239398560854290237064523445340691655877348865923425346786261961110586283
      Line 22614, in log /nightly/current_run/scratch/master/ac_range_check-sim-xcelium/0.ac_range_check_stress_all/latest/run.log

        UVM_ERROR @ 9471861106 ps: (ac_range_check_scoreboard.sv:362) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
        UVM_INFO @ 9471861106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.42671275176784692984319747024810555626397870797052817547646680732705736859262
      Line 123, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1092000286ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1092000286ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.41344331566190525767009992946059073700451238252557881801156232043991610459137
      Line 403, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 411843667 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 411843667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.89937589973631709365674578153312764046831920731915200834751541915956025160545
      Line 148, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 485497598 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 485497598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:

  • Test gpio_stress_all_with_rand_reset has 1 failures.

    • 0.gpio_stress_all_with_rand_reset.100938422269178967555506536454739677941546424602982815158950034851927973715430
      Line 358, in log /nightly/current_run/scratch/master/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 851367437 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
        UVM_INFO @ 851367437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:

  • Test kmac_key_error has 1 failures.

    • 0.kmac_key_error.34893350856584126097929721296551151832084030273684758863521088628446468801750
      Line 92, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_key_error/latest/run.log

        UVM_ERROR @ 9427328549 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
        UVM_INFO @ 9427328549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.58067474621097935421167350826248821592577899889846946177687138101474247280056
      Line 183, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 11590211ps failed at 11590211ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 11590211ps failed at 11590211ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_partition_walk has 1 failures.

    • 0.otp_ctrl_partition_walk.52539890091598712248487623677105593298164984335457877977747145325611917572096
      Line 112518, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest/run.log

        UVM_ERROR @ 13327476401 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_partition_walk_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 16080 [0x3ed0]) dai addr 3ed0 rdata0 readout mismatch
        UVM_INFO @ 13327476401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_low_freq_read has 1 failures.

    • 0.otp_ctrl_low_freq_read.72105312599366725211376745596791334925406467821063004500174044296156987349294
      Line 86, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest/run.log

        UVM_ERROR @ 58917356479 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
        UVM_INFO @ 58917356479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 1 failures:

  • Test otp_ctrl_check_fail has 1 failures.

    • 0.otp_ctrl_check_fail.12771757421335994751650713521137313306290074459197732532962479101740521362772
      Line 9269, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest/run.log

        UVM_ERROR @ 13743913909 ps: (otp_ctrl_scoreboard.sv:1250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1333989368 [0x4f830ff8] vs 1333989112 [0x4f830ef8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 13743913909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.114482830112241625271597834236130928082011656553990563667304528512610949354318
      Line 93, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  37666201 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
        UVM_INFO @  37666201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire has 1 failures:

  • Test otp_ctrl_sec_cm has 1 failures.

    • 0.otp_ctrl_sec_cm.32945626007370172965073247366136946013506553134734759467133807191013030698799
      Line 1623, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest/run.log

        UVM_ERROR @ 27197587515 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
        UVM_INFO @ 27197587515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::ext_csr_wr_operational_state_cg@*_*.csr_cp) is an illegal value. has 1 failures:

  • Test otbn_smoke has 1 failures.

    • 0.otbn_smoke.59578663792391610131259079574816229521338605230633732873264146777550737930561
      Line 114, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 564):(Time: 126785136 PS + 17) Sampled value (8591112127431472442413084276077) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::ext_csr_wr_operational_state_cg@4191_1.csr_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 564):(Time: 132243513 PS + 17) Sampled value (8591112127431472442413084276077) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::ext_csr_wr_operational_state_cg@4191_1.csr_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 564):(Time: 138160227 PS + 17) Sampled value (8591112127431472442413084276077) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::ext_csr_wr_operational_state_cg@4191_1.csr_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 564):(Time: 140618580 PS + 17) Sampled value (8591112127431472442413084276077) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::ext_csr_wr_operational_state_cg@4191_1.csr_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 564):(Time: 145993623 PS + 17) Sampled value (8591112127431472442413084276077) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::ext_csr_wr_operational_state_cg@4191_1.csr_cp) is an illegal value.
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_u_cg@*_*.mnemonic_cp) is an illegal value. has 1 failures:

  • Test otbn_controller_ispr_rdata_err has 1 failures.

    • 0.otbn_controller_ispr_rdata_err.89417532338632797301838694852397064138684082000874986823856485927751124217649
      Line 102, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_controller_ispr_rdata_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1332):(Time: 4024668 PS + 23) Sampled value (7107945) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_u_cg@4224_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 4034977 PS + 24) Sampled value (7107945) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 4034977 PS + 24) Sampled value (6385252) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 4034977 PS + 24) Sampled value (6385252) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1462):(Time: 4034977 PS + 24) Sampled value (6385252) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_log_binop_cg@4233_1.mnemonic_cp) is an illegal value.
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_bnxid_cg@*_*.mnemonic_cp) is an illegal value. has 1 failures:

  • Test otbn_urnd_err has 1 failures.

    • 0.otbn_urnd_err.75636498574802553570857048452398621761006244890033434980180023779295262464257
      Line 104, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_urnd_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1122):(Time: 42573686 PS + 21) Sampled value (108225364781412) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_bnxid_cg@4213_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1956):(Time: 42573686 PS + 21) Sampled value (108225364781412) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_bn_xid_cg@4247_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 42684797 PS + 33) Sampled value (108225364781412) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 42684797 PS + 33) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 42684797 PS + 33) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
      

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.9883410707323146678651549816490752883918641077635782506345799521891819124906
      Line 95, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 57691496 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 57691496 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 57691496 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 57691496 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 57691496 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
      

• Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 0.chip_tl_errors.26880954719097818930029317243950431553474517981419149105872641328536777294861
      Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

            Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
        UVM_ERROR @ 118.025000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
        UVM_INFO @ 118.025000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:

  • Test chip_rv_dm_lc_disabled has 1 failures.

    • 0.chip_rv_dm_lc_disabled.64372183725668009692989984822079919056523838400783679462531073037630419289652
      Line 216, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

        UVM_ERROR @ 123.363000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x406a8 read out mismatch
        UVM_INFO @ 123.363000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:

  • Test chip_sw_example_rom has 1 failures.

    • 0.chip_sw_example_rom.69226866259329132605681907918544982760216342264417375418576450606464670526482
      Line 537, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

        UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
        UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:

  • Test chip_sw_spi_device_pass_through_collision has 1 failures.

    • 0.chip_sw_spi_device_pass_through_collision.94580208104771458865629314424759397376606430841336455074640891181545531367659
      Line 435, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_ERROR @ 267.760000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
        UVM_INFO @ 267.760000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 1 failures:

  • Test chip_sw_rstmgr_alert_info has 1 failures.

    • 0.chip_sw_rstmgr_alert_info.45440793768568564690716491120017062402773188414137817321636383715332070804811
      Line 443, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

        UVM_ERROR @ 290.073000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
        UVM_INFO @ 290.073000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:

  • Test chip_sw_soc_proxy_external_wakeup has 1 failures.

    • 0.chip_sw_soc_proxy_external_wakeup.1543832600110733504841503206590581842249699913199197064024467747025583471198
      Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log

        UVM_ERROR @ 138.836000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
        UVM_INFO @ 138.836000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns * has 1 failures:

  • Test chip_sw_soc_proxy_gpios has 1 failures.

    • 0.chip_sw_soc_proxy_gpios.15019125405873079233471125726893415287806256927351836394737275602258905957685
      Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log

        UVM_ERROR @ 136.457000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
        UVM_INFO @ 136.457000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 1 failures:

  • Test chip_sw_aon_timer_irq has 1 failures.

    • 0.chip_sw_aon_timer_irq.101944738666017911211829193138944795991176507558557074648438077396266437068912
      Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

        UVM_ERROR @ 559.554000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4189 usec which is not in the range 382 usec and 437 usec
        UVM_INFO @ 559.554000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:

  • Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.

    • 0.chip_sw_aon_timer_wdog_bite_reset.6973565840081890580466980159545587593406547314626106909596733901275081836591
      Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log

        UVM_ERROR @ 164.292000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
        UVM_INFO @ 164.292000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:

  • Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.

    • 0.chip_sw_rv_core_ibex_nmi_irq.3436375601755246953868896351571439718416841229673914094902231294295105842222
      Line 417, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log

        UVM_ERROR @ 251.579000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
        UVM_INFO @ 251.579000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:

  • Test chip_sw_kmac_app_rom has 1 failures.

    • 0.chip_sw_kmac_app_rom.82832748560314967274738951836190777878915904918041431971431031678835789738696
      Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log

        UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
        UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:

  • Test chip_sw_dma_abort has 1 failures.

    • 0.chip_sw_dma_abort.15284937760519718198168464355746213593967223608795544639053699257779038174461
      Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

        UVM_FATAL @ 165.440000 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
        UVM_INFO @ 165.440000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:

  • Test chip_padctrl_attributes has 1 failures.

    • 0.chip_padctrl_attributes.60665553523586762691594509019598108199100222597956025273112037994388396527956
      Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.