AES/UNMASKED Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	58.049us	2	2	100.00
V1	smoke	aes_smoke	3.000s	69.617us	2	2	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	61.227us	2	2	100.00
V1	csr_rw	aes_csr_rw	2.000s	81.088us	2	2	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	1847.973us	2	2	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	100.521us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	88.325us	2	2	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	81.088us	2	2	100.00
		aes_csr_aliasing	3.000s	100.521us	2	2	100.00
V1		TOTAL			14	14	100.00
V2	algorithm	aes_smoke	3.000s	69.617us	2	2	100.00
		aes_config_error	3.000s	63.989us	2	2	100.00
		aes_stress	5.000s	272.142us	2	2	100.00
V2	key_length	aes_smoke	3.000s	69.617us	2	2	100.00
		aes_config_error	3.000s	63.989us	2	2	100.00
		aes_stress	5.000s	272.142us	2	2	100.00
V2	back2back	aes_stress	5.000s	272.142us	2	2	100.00
		aes_b2b	10.000s	313.152us	2	2	100.00
V2	backpressure	aes_stress	5.000s	272.142us	2	2	100.00
V2	multi_message	aes_smoke	3.000s	69.617us	2	2	100.00
		aes_config_error	3.000s	63.989us	2	2	100.00
		aes_stress	5.000s	272.142us	2	2	100.00
		aes_alert_reset	6.000s	666.063us	2	2	100.00
V2	failure_test	aes_man_cfg_err	2.000s	70.115us	2	2	100.00
		aes_config_error	3.000s	63.989us	2	2	100.00
		aes_alert_reset	6.000s	666.063us	2	2	100.00
V2	trigger_clear_test	aes_clear	3.000s	147.324us	2	2	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	335.059us	2	2	100.00
V2	reset_recovery	aes_alert_reset	6.000s	666.063us	2	2	100.00
V2	stress	aes_stress	5.000s	272.142us	2	2	100.00
V2	sideload	aes_stress	5.000s	272.142us	2	2	100.00
		aes_sideload	3.000s	84.856us	2	2	100.00
V2	deinitialization	aes_deinit	3.000s	265.870us	2	2	100.00
V2	stress_all	aes_stress_all	13.000s	1454.908us	2	2	100.00
V2	alert_test	aes_alert_test	2.000s	103.873us	2	2	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	104.510us	2	2	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	104.510us	2	2	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	61.227us	2	2	100.00
		aes_csr_rw	2.000s	81.088us	2	2	100.00
		aes_csr_aliasing	3.000s	100.521us	2	2	100.00
		aes_same_csr_outstanding	2.000s	192.411us	2	2	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	61.227us	2	2	100.00
		aes_csr_rw	2.000s	81.088us	2	2	100.00
		aes_csr_aliasing	3.000s	100.521us	2	2	100.00
		aes_same_csr_outstanding	2.000s	192.411us	2	2	100.00
V2		TOTAL			26	26	100.00
V2S	reseeding	aes_reseed	5.000s	249.697us	2	2	100.00
V2S	fault_inject	aes_fi	5.000s	815.385us	2	2	100.00
		aes_control_fi	2.000s	56.325us	2	2	100.00
		aes_cipher_fi	2.000s	88.078us	2	2	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	146.275us	2	2	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	146.275us	2	2	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	146.275us	2	2	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	146.275us	2	2	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	485.365us	2	2	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	3391.542us	2	2	100.00
		aes_tl_intg_err	2.000s	188.221us	2	2	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.000s	188.221us	2	2	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	666.063us	2	2	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	146.275us	2	2	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	69.617us	2	2	100.00
		aes_stress	5.000s	272.142us	2	2	100.00
		aes_alert_reset	6.000s	666.063us	2	2	100.00
		aes_core_fi	3.000s	68.912us	2	2	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	146.275us	2	2	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	101.551us	2	2	100.00
		aes_stress	5.000s	272.142us	2	2	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	272.142us	2	2	100.00
		aes_sideload	3.000s	84.856us	2	2	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	101.551us	2	2	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	101.551us	2	2	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	101.551us	2	2	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	101.551us	2	2	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	101.551us	2	2	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	272.142us	2	2	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	272.142us	2	2	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	815.385us	2	2	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	815.385us	2	2	100.00
		aes_control_fi	2.000s	56.325us	2	2	100.00
		aes_cipher_fi	2.000s	88.078us	2	2	100.00
		aes_ctr_fi	2.000s	63.925us	2	2	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	815.385us	2	2	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	815.385us	2	2	100.00
		aes_control_fi	2.000s	56.325us	2	2	100.00
		aes_cipher_fi	2.000s	88.078us	2	2	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	2.000s	88.078us	2	2	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	815.385us	2	2	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	815.385us	2	2	100.00
		aes_control_fi	2.000s	56.325us	2	2	100.00
		aes_ctr_fi	2.000s	63.925us	2	2	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	815.385us	2	2	100.00
		aes_control_fi	2.000s	56.325us	2	2	100.00
		aes_cipher_fi	2.000s	88.078us	2	2	100.00
		aes_ctr_fi	2.000s	63.925us	2	2	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	666.063us	2	2	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	815.385us	2	2	100.00
		aes_control_fi	2.000s	56.325us	2	2	100.00
		aes_cipher_fi	2.000s	88.078us	2	2	100.00
		aes_ctr_fi	2.000s	63.925us	2	2	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	815.385us	2	2	100.00
		aes_control_fi	2.000s	56.325us	2	2	100.00
		aes_cipher_fi	2.000s	88.078us	2	2	100.00
		aes_ctr_fi	2.000s	63.925us	2	2	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	815.385us	2	2	100.00
		aes_control_fi	2.000s	56.325us	2	2	100.00
		aes_ctr_fi	2.000s	63.925us	2	2	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	815.385us	2	2	100.00
		aes_control_fi	2.000s	56.325us	2	2	100.00
		aes_cipher_fi	2.000s	88.078us	2	2	100.00
V2S		TOTAL			22	22	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	17.000s	1602.304us	0	2	0.00
V3		TOTAL			0	2	0.00
		TOTAL			62	64	96.88

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.94	92.64	85.93	94.44	86.17	97.99	91.11	97.69	80.08

Failure Buckets

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.66889971081189241574720228001473431077685132672540615231414860425837517241205
      Line 324, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  72737721 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @  72737721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.70337861810081985144007991198551823672019202537185864489686454773923746620711
      Line 720, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 1602303990 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 1602303990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---