CSRNG Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 3.000s 36.577us 1 1 100.00
V1 csr_hw_reset csrng_csr_hw_reset 3.000s 39.608us 1 1 100.00
V1 csr_rw csrng_csr_rw 2.000s 38.090us 1 1 100.00
V1 csr_bit_bash csrng_csr_bit_bash 19.000s 592.526us 1 1 100.00
V1 csr_aliasing csrng_csr_aliasing 3.000s 53.209us 1 1 100.00
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 2.000s 32.406us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 2.000s 38.090us 1 1 100.00
csrng_csr_aliasing 3.000s 53.209us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 interrupts csrng_intr 6.000s 270.080us 1 1 100.00
V2 alerts csrng_alert 7.000s 356.590us 1 1 100.00
V2 err csrng_err 2.000s 25.333us 1 1 100.00
V2 cmds csrng_cmds 39.000s 1732.377us 1 1 100.00
V2 life cycle csrng_cmds 39.000s 1732.377us 1 1 100.00
V2 stress_all csrng_stress_all 1109.000s 90323.961us 1 1 100.00
V2 intr_test csrng_intr_test 2.000s 25.595us 1 1 100.00
V2 alert_test csrng_alert_test 3.000s 16.940us 1 1 100.00
V2 tl_d_oob_addr_access csrng_tl_errors 4.000s 75.457us 1 1 100.00
V2 tl_d_illegal_access csrng_tl_errors 4.000s 75.457us 1 1 100.00
V2 tl_d_outstanding_access csrng_csr_hw_reset 3.000s 39.608us 1 1 100.00
csrng_csr_rw 2.000s 38.090us 1 1 100.00
csrng_csr_aliasing 3.000s 53.209us 1 1 100.00
csrng_same_csr_outstanding 5.000s 294.713us 1 1 100.00
V2 tl_d_partial_access csrng_csr_hw_reset 3.000s 39.608us 1 1 100.00
csrng_csr_rw 2.000s 38.090us 1 1 100.00
csrng_csr_aliasing 3.000s 53.209us 1 1 100.00
csrng_same_csr_outstanding 5.000s 294.713us 1 1 100.00
V2 TOTAL 9 9 100.00
V2S tl_intg_err csrng_tl_intg_err 5.000s 118.310us 1 1 100.00
csrng_sec_cm 3.000s 61.768us 1 1 100.00
V2S sec_cm_config_regwen csrng_csr_rw 2.000s 38.090us 1 1 100.00
csrng_regwen 2.000s 16.893us 1 1 100.00
V2S sec_cm_config_mubi csrng_alert 7.000s 356.590us 1 1 100.00
V2S sec_cm_intersig_mubi csrng_stress_all 1109.000s 90323.961us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
csrng_sec_cm 3.000s 61.768us 1 1 100.00
V2S sec_cm_updrsp_fsm_sparse csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
csrng_sec_cm 3.000s 61.768us 1 1 100.00
V2S sec_cm_update_fsm_sparse csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
csrng_sec_cm 3.000s 61.768us 1 1 100.00
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
csrng_sec_cm 3.000s 61.768us 1 1 100.00
V2S sec_cm_outblk_fsm_sparse csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
csrng_sec_cm 3.000s 61.768us 1 1 100.00
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
csrng_sec_cm 3.000s 61.768us 1 1 100.00
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
csrng_sec_cm 3.000s 61.768us 1 1 100.00
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
csrng_sec_cm 3.000s 61.768us 1 1 100.00
V2S sec_cm_ctrl_mubi csrng_alert 7.000s 356.590us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
V2S sec_cm_constants_lc_gated csrng_stress_all 1109.000s 90323.961us 1 1 100.00
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 7.000s 356.590us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 5.000s 118.310us 1 1 100.00
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
csrng_sec_cm 3.000s 61.768us 1 1 100.00
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
csrng_sec_cm 3.000s 61.768us 1 1 100.00
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 6.000s 270.080us 1 1 100.00
csrng_err 2.000s 25.333us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 214.000s 19133.358us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
94.46 96.53 91.49 97.49 94.65 91.53 66.67 92.18 76.76