DMA Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	4.000s	527.513us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	4.000s	383.724us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	5.000s	1413.769us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	85.095us	1	1	100.00
V1	csr_rw	dma_csr_rw	1.000s	48.938us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	5.000s	2907.327us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	4.000s	2848.315us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	80.503us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	1.000s	48.938us	1	1	100.00
		dma_csr_aliasing	4.000s	2848.315us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	21.000s	1662.005us	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	249.000s	40861.380us	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	447.000s	44259.755us	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	447.000s	44259.755us	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	249.000s	40861.380us	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	1091.000s	179263.210us	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	447.000s	44259.755us	1	1	100.00
V2	dma_abort	dma_abort	14.000s	2180.364us	1	1	100.00
V2	dma_stress_all	dma_stress_all	172.000s	14449.386us	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	40.020us	1	1	100.00
V2	intr_test	dma_intr_test	2.000s	15.627us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	3.000s	477.864us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	3.000s	477.864us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	85.095us	1	1	100.00
		dma_csr_rw	1.000s	48.938us	1	1	100.00
		dma_csr_aliasing	4.000s	2848.315us	1	1	100.00
		dma_same_csr_outstanding	2.000s	65.033us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	85.095us	1	1	100.00
		dma_csr_rw	1.000s	48.938us	1	1	100.00
		dma_csr_aliasing	4.000s	2848.315us	1	1	100.00
		dma_same_csr_outstanding	2.000s	65.033us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	9.000s	274.586us	1	1	100.00
		dma_generic_stress	1091.000s	179263.210us	1	1	100.00
		dma_handshake_stress	447.000s	44259.755us	1	1	100.00
V2S	dma_config_lock	dma_config_lock	6.000s	313.945us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	117.776us	1	1	100.00
		dma_sec_cm	2.000s	65.006us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	44.000s	3748.405us	1	1	100.00
		dma_longer_transfer	6.000s	1445.547us	1	1	100.00
		dma_stress_all_with_rand_reset	7.000s	908.858us	0	1	0.00
		TOTAL			24	25	96.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
88.81	97.38	95.83	96.89	94.06	83.12	91.55	95.97	60.73

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.104848212773440521729144906863994352957991932722874419652909467107756599496654
      Line 95, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  908858467ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  908858467ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---