HMAC Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	9.850s	0.000us	1	1	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.140s	0.000us	1	1	100.00
V1	csr_rw	hmac_csr_rw	0.890s	0.000us	1	1	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	4.380s	0.000us	1	1	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.090s	0.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	761.820s	0.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.890s	0.000us	1	1	100.00
		hmac_csr_aliasing	2.090s	0.000us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	long_msg	hmac_long_msg	21.550s	0.000us	1	1	100.00
V2	back_pressure	hmac_back_pressure	55.460s	0.000us	1	1	100.00
V2	test_vectors	hmac_test_sha256_vectors	186.650s	0.000us	1	1	100.00
		hmac_test_sha384_vectors	400.110s	0.000us	1	1	100.00
		hmac_test_sha512_vectors	378.120s	0.000us	1	1	100.00
		hmac_test_hmac256_vectors	7.690s	0.000us	1	1	100.00
		hmac_test_hmac384_vectors	10.200s	0.000us	1	1	100.00
		hmac_test_hmac512_vectors	11.790s	0.000us	1	1	100.00
V2	burst_wr	hmac_burst_wr	18.920s	0.000us	1	1	100.00
V2	datapath_stress	hmac_datapath_stress	400.500s	0.000us	1	1	100.00
V2	error	hmac_error	77.660s	0.000us	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	18.380s	0.000us	1	1	100.00
V2	save_and_restore	hmac_smoke	9.850s	0.000us	1	1	100.00
		hmac_long_msg	21.550s	0.000us	1	1	100.00
		hmac_back_pressure	55.460s	0.000us	1	1	100.00
		hmac_datapath_stress	400.500s	0.000us	1	1	100.00
		hmac_burst_wr	18.920s	0.000us	1	1	100.00
		hmac_stress_all	168.890s	0.000us	1	1	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	9.850s	0.000us	1	1	100.00
		hmac_long_msg	21.550s	0.000us	1	1	100.00
		hmac_back_pressure	55.460s	0.000us	1	1	100.00
		hmac_datapath_stress	400.500s	0.000us	1	1	100.00
		hmac_wipe_secret	18.380s	0.000us	1	1	100.00
		hmac_test_sha256_vectors	186.650s	0.000us	1	1	100.00
		hmac_test_sha384_vectors	400.110s	0.000us	1	1	100.00
		hmac_test_sha512_vectors	378.120s	0.000us	1	1	100.00
		hmac_test_hmac256_vectors	7.690s	0.000us	1	1	100.00
		hmac_test_hmac384_vectors	10.200s	0.000us	1	1	100.00
		hmac_test_hmac512_vectors	11.790s	0.000us	1	1	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	9.850s	0.000us	1	1	100.00
		hmac_long_msg	21.550s	0.000us	1	1	100.00
		hmac_back_pressure	55.460s	0.000us	1	1	100.00
		hmac_datapath_stress	400.500s	0.000us	1	1	100.00
		hmac_burst_wr	18.920s	0.000us	1	1	100.00
		hmac_error	77.660s	0.000us	1	1	100.00
		hmac_wipe_secret	18.380s	0.000us	1	1	100.00
		hmac_test_sha256_vectors	186.650s	0.000us	1	1	100.00
		hmac_test_sha384_vectors	400.110s	0.000us	1	1	100.00
		hmac_test_sha512_vectors	378.120s	0.000us	1	1	100.00
		hmac_test_hmac256_vectors	7.690s	0.000us	1	1	100.00
		hmac_test_hmac384_vectors	10.200s	0.000us	1	1	100.00
		hmac_test_hmac512_vectors	11.790s	0.000us	1	1	100.00
		hmac_stress_all	168.890s	0.000us	1	1	100.00
V2	stress_all	hmac_stress_all	168.890s	0.000us	1	1	100.00
V2	alert_test	hmac_alert_test	0.550s	0.000us	1	1	100.00
V2	intr_test	hmac_intr_test	0.780s	0.000us	1	1	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.020s	0.000us	1	1	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.020s	0.000us	1	1	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.140s	0.000us	1	1	100.00
		hmac_csr_rw	0.890s	0.000us	1	1	100.00
		hmac_csr_aliasing	2.090s	0.000us	1	1	100.00
		hmac_same_csr_outstanding	1.710s	0.000us	1	1	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.140s	0.000us	1	1	100.00
		hmac_csr_rw	0.890s	0.000us	1	1	100.00
		hmac_csr_aliasing	2.090s	0.000us	1	1	100.00
		hmac_same_csr_outstanding	1.710s	0.000us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	tl_intg_err	hmac_sec_cm	0.870s	0.000us	1	1	100.00
		hmac_tl_intg_err	2.180s	0.000us	1	1	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.180s	0.000us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	9.850s	0.000us	1	1	100.00
V3	stress_reset	hmac_stress_reset	2.180s	0.000us	1	1	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	7.460s	0.000us	1	1	100.00
V3		TOTAL			2	2	100.00
	Unmapped tests	hmac_directed	1.880s	0.000us	1	1	100.00
		TOTAL			28	28	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.94	99.74	95.84	100.00	94.12	99.17	96.42	44.28