I2C Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	33.480s	0.000us	1	1	100.00
V1	target_smoke	i2c_target_smoke	11.520s	0.000us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.930s	0.000us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.900s	0.000us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.330s	0.000us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.380s	0.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.920s	0.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.900s	0.000us	1	1	100.00
		i2c_csr_aliasing	1.380s	0.000us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.830s	0.000us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	194.700s	0.000us	0	1	0.00
V2	host_maxperf	i2c_host_perf	110.810s	0.000us	1	1	100.00
V2	host_override	i2c_host_override	0.840s	0.000us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	86.930s	0.000us	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	31.580s	0.000us	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.600s	0.000us	1	1	100.00
		i2c_host_fifo_fmt_empty	12.470s	0.000us	1	1	100.00
		i2c_host_fifo_reset_rx	4.000s	0.000us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	65.370s	0.000us	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	8.180s	0.000us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.810s	0.000us	0	1	0.00
V2	target_glitch	i2c_target_glitch	3.640s	0.000us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	348.630s	0.000us	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.780s	0.000us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	3.080s	0.000us	1	1	100.00
		i2c_target_intr_smoke	2.680s	0.000us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.120s	0.000us	1	1	100.00
		i2c_target_fifo_reset_tx	1.250s	0.000us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	131.050s	0.000us	1	1	100.00
		i2c_target_stress_rd	3.080s	0.000us	1	1	100.00
		i2c_target_intr_stress_wr	840.840s	0.000us	1	1	100.00
V2	target_timeout	i2c_target_timeout	7.060s	0.000us	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	8.400s	0.000us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.920s	0.000us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.140s	0.000us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.550s	0.000us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.180s	0.000us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	110.810s	0.000us	1	1	100.00
		i2c_host_perf_precise	1.280s	0.000us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	8.180s	0.000us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.400s	0.000us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.600s	0.000us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.280s	0.000us	1	1	100.00
		i2c_target_nack_txstretch	1.120s	0.000us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.590s	0.000us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.860s	0.000us	1	1	100.00
V2	alert_test	i2c_alert_test	0.860s	0.000us	1	1	100.00
V2	intr_test	i2c_intr_test	0.670s	0.000us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.140s	0.000us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.140s	0.000us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.930s	0.000us	1	1	100.00
		i2c_csr_rw	0.900s	0.000us	1	1	100.00
		i2c_csr_aliasing	1.380s	0.000us	1	1	100.00
		i2c_same_csr_outstanding	0.830s	0.000us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.930s	0.000us	1	1	100.00
		i2c_csr_rw	0.900s	0.000us	1	1	100.00
		i2c_csr_aliasing	1.380s	0.000us	1	1	100.00
		i2c_same_csr_outstanding	0.830s	0.000us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.720s	0.000us	1	1	100.00
		i2c_sec_cm	0.920s	0.000us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.720s	0.000us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	2.470s	0.000us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.000s	0.000us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	14.650s	0.000us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.85	96.41	84.74	89.66	44.05	92.33	93.02	79.70

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.80800072883785720512078932464219382013008208994152410412241359354925542354090
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  44615283 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  44615283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.43536464235575607938562762207891280129811005876624060135131674260511125172977
      Line 113, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 8055693056 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 8055693056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.6252378002456709798606380842637842315573484900803725053944914414145663647874
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 3596810710 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 3596810710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.51210677768583753596112077573542204122698296089401878407128843814319527823866
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  26741599 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @  26741599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.25859384403717340974204975870298739006497600709857798326504202368196392963808
      Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 228929984 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 228929984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.51651009960381855818514000510994316885494427683512905744963228682959903138555
      Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 556146145 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 556146145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.47936628629417786299622328262676344913350226650980313620853874035638680770383
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 380484376 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @22280