KEYMGR Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 22.100s 0.000us 1 1 100.00
V1 random keymgr_random 4.610s 0.000us 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.510s 0.000us 1 1 100.00
V1 csr_rw keymgr_csr_rw 1.070s 0.000us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 5.410s 0.000us 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 5.570s 0.000us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.670s 0.000us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.070s 0.000us 1 1 100.00
keymgr_csr_aliasing 5.570s 0.000us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 25.430s 0.000us 1 1 100.00
V2 sideload keymgr_sideload 23.620s 0.000us 1 1 100.00
keymgr_sideload_kmac 14.340s 0.000us 1 1 100.00
keymgr_sideload_aes 3.250s 0.000us 1 1 100.00
keymgr_sideload_otbn 4.320s 0.000us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 3.780s 0.000us 1 1 100.00
V2 lc_disable keymgr_lc_disable 3.560s 0.000us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 3.040s 0.000us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 3.360s 0.000us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 3.160s 0.000us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 1.750s 0.000us 1 1 100.00
V2 stress_all keymgr_stress_all 8.640s 0.000us 1 1 100.00
V2 intr_test keymgr_intr_test 0.740s 0.000us 1 1 100.00
V2 alert_test keymgr_alert_test 0.730s 0.000us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 2.440s 0.000us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 2.440s 0.000us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.510s 0.000us 1 1 100.00
keymgr_csr_rw 1.070s 0.000us 1 1 100.00
keymgr_csr_aliasing 5.570s 0.000us 1 1 100.00
keymgr_same_csr_outstanding 1.640s 0.000us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.510s 0.000us 1 1 100.00
keymgr_csr_rw 1.070s 0.000us 1 1 100.00
keymgr_csr_aliasing 5.570s 0.000us 1 1 100.00
keymgr_same_csr_outstanding 1.640s 0.000us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 9.170s 0.000us 1 1 100.00
V2S tl_intg_err keymgr_tl_intg_err 3.820s 0.000us 1 1 100.00
keymgr_sec_cm 9.170s 0.000us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 2.110s 0.000us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 2.110s 0.000us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 2.110s 0.000us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 2.110s 0.000us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 4.840s 0.000us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 9.170s 0.000us 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 9.170s 0.000us 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 3.820s 0.000us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 2.110s 0.000us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 25.430s 0.000us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_csr_rw 1.070s 0.000us 1 1 100.00
keymgr_random 4.610s 0.000us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_csr_rw 1.070s 0.000us 1 1 100.00
keymgr_random 4.610s 0.000us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_csr_rw 1.070s 0.000us 1 1 100.00
keymgr_random 4.610s 0.000us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 3.560s 0.000us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 3.160s 0.000us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 3.160s 0.000us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 4.610s 0.000us 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 2.310s 0.000us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 9.170s 0.000us 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 9.170s 0.000us 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 9.170s 0.000us 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 3.770s 0.000us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 3.560s 0.000us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 9.170s 0.000us 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 9.170s 0.000us 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 9.170s 0.000us 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 3.770s 0.000us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 3.770s 0.000us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 9.170s 0.000us 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 3.770s 0.000us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 9.170s 0.000us 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 3.770s 0.000us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 11.200s 0.000us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
91.08 98.70 95.15 97.80 86.05 97.67 97.48 64.71