KEYMGR_DPE Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	25.730s	0.000us	1	1	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	0.850s	0.000us	1	1	100.00
V1	csr_rw	keymgr_dpe_csr_rw	0.900s	0.000us	1	1	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	6.860s	0.000us	1	1	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	2.290s	0.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.210s	0.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	0.900s	0.000us	1	1	100.00
		keymgr_dpe_csr_aliasing	2.290s	0.000us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	intr_test	keymgr_dpe_intr_test	0.900s	0.000us	1	1	100.00
V2	alert_test	keymgr_dpe_alert_test	0.820s	0.000us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	1.960s	0.000us	1	1	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	1.960s	0.000us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	0.850s	0.000us	1	1	100.00
		keymgr_dpe_csr_rw	0.900s	0.000us	1	1	100.00
		keymgr_dpe_csr_aliasing	2.290s	0.000us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	1.510s	0.000us	1	1	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	0.850s	0.000us	1	1	100.00
		keymgr_dpe_csr_rw	0.900s	0.000us	1	1	100.00
		keymgr_dpe_csr_aliasing	2.290s	0.000us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	1.510s	0.000us	1	1	100.00
V2		TOTAL			4	4	100.00
V2S	tl_intg_err	keymgr_dpe_tl_intg_err	2.650s	0.000us	1	1	100.00
		keymgr_dpe_sec_cm	7.900s	0.000us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	1.200s	0.000us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	1.200s	0.000us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	1.200s	0.000us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	1.200s	0.000us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	2.980s	0.000us	1	1	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	7.900s	0.000us	1	1	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	7.900s	0.000us	1	1	100.00
V2S		TOTAL			4	4	100.00
		TOTAL			14	14	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.15	97.50	88.93	63.15	75.68	94.42	97.39	16.00