KMAC/MASKED Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 36.730s 0.000us 2 2 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.150s 0.000us 2 2 100.00
V1 csr_rw kmac_csr_rw 1.190s 0.000us 2 2 100.00
V1 csr_bit_bash kmac_csr_bit_bash 10.890s 0.000us 2 2 100.00
V1 csr_aliasing kmac_csr_aliasing 6.890s 0.000us 2 2 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 1.760s 0.000us 2 2 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.190s 0.000us 2 2 100.00
kmac_csr_aliasing 6.890s 0.000us 2 2 100.00
V1 mem_walk kmac_mem_walk 1.010s 0.000us 2 2 100.00
V1 mem_partial_access kmac_mem_partial_access 1.410s 0.000us 2 2 100.00
V1 TOTAL 16 16 100.00
V2 long_msg_and_output kmac_long_msg_and_output 2116.690s 0.000us 2 2 100.00
V2 burst_write kmac_burst_write 748.480s 0.000us 2 2 100.00
V2 test_vectors kmac_test_vectors_sha3_224 1286.000s 0.000us 2 2 100.00
kmac_test_vectors_sha3_256 1742.760s 0.000us 2 2 100.00
kmac_test_vectors_sha3_384 1415.920s 0.000us 2 2 100.00
kmac_test_vectors_sha3_512 951.250s 0.000us 2 2 100.00
kmac_test_vectors_shake_128 1789.670s 0.000us 2 2 100.00
kmac_test_vectors_shake_256 1419.830s 0.000us 2 2 100.00
kmac_test_vectors_kmac 2.400s 0.000us 2 2 100.00
kmac_test_vectors_kmac_xof 2.700s 0.000us 2 2 100.00
V2 sideload kmac_sideload 350.080s 0.000us 2 2 100.00
V2 app kmac_app 180.200s 0.000us 2 2 100.00
V2 app_with_partial_data kmac_app_with_partial_data 10.280s 0.000us 2 2 100.00
V2 entropy_refresh kmac_entropy_refresh 150.590s 0.000us 2 2 100.00
V2 error kmac_error 213.830s 0.000us 2 2 100.00
V2 key_error kmac_key_error 8.890s 0.000us 2 2 100.00
V2 sideload_invalid kmac_sideload_invalid 2.850s 0.000us 2 2 100.00
V2 edn_timeout_error kmac_edn_timeout_error 10.750s 0.000us 2 2 100.00
V2 entropy_mode_error kmac_entropy_mode_error 16.970s 0.000us 2 2 100.00
V2 entropy_ready_error kmac_entropy_ready_error 32.970s 0.000us 2 2 100.00
V2 lc_escalation kmac_lc_escalation 2.040s 0.000us 2 2 100.00
V2 stress_all kmac_stress_all 1276.750s 0.000us 2 2 100.00
V2 intr_test kmac_intr_test 0.980s 0.000us 2 2 100.00
V2 alert_test kmac_alert_test 0.970s 0.000us 2 2 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 2.740s 0.000us 2 2 100.00
V2 tl_d_illegal_access kmac_tl_errors 2.740s 0.000us 2 2 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.150s 0.000us 2 2 100.00
kmac_csr_rw 1.190s 0.000us 2 2 100.00
kmac_csr_aliasing 6.890s 0.000us 2 2 100.00
kmac_same_csr_outstanding 1.640s 0.000us 2 2 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.150s 0.000us 2 2 100.00
kmac_csr_rw 1.190s 0.000us 2 2 100.00
kmac_csr_aliasing 6.890s 0.000us 2 2 100.00
kmac_same_csr_outstanding 1.640s 0.000us 2 2 100.00
V2 TOTAL 52 52 100.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.900s 0.000us 2 2 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.900s 0.000us 2 2 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.900s 0.000us 2 2 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.900s 0.000us 2 2 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 4.760s 0.000us 2 2 100.00
V2S tl_intg_err kmac_tl_intg_err 3.410s 0.000us 2 2 100.00
kmac_sec_cm 37.310s 0.000us 2 2 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 3.410s 0.000us 2 2 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 2.040s 0.000us 2 2 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 36.730s 0.000us 2 2 100.00
V2S sec_cm_key_sideload kmac_sideload 350.080s 0.000us 2 2 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.900s 0.000us 2 2 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 37.310s 0.000us 2 2 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 37.310s 0.000us 2 2 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 37.310s 0.000us 2 2 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 36.730s 0.000us 2 2 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 2.040s 0.000us 2 2 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 37.310s 0.000us 2 2 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 153.330s 0.000us 2 2 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 36.730s 0.000us 2 2 100.00
V2S TOTAL 10 10 100.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 120.530s 0.000us 2 2 100.00
V3 TOTAL 2 2 100.00
TOTAL 80 80 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
91.97 98.89 93.56 99.43 64.08 96.58 97.67 93.57