33c2274| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 55.000s | 16640.360us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 1.000s | 40.956us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 1.000s | 15.705us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 3.000s | 174.584us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 2.000s | 23.812us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 1.000s | 161.279us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 1.000s | 15.705us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 2.000s | 23.812us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | mbx_stress | mbx_stress | 12.000s | 1901.314us | 0 | 1 | 0.00 |
| V2 | mbx_max_activity | mbx_stress_zero_delays | 59.000s | 6823.656us | 1 | 1 | 100.00 |
| V2 | mbx_imbx_oob | mbx_imbx_oob | 35.000s | 15015.979us | 1 | 1 | 100.00 |
| V2 | mbx_doe_intr_msg | mbx_doe_intr_msg | 18.000s | 3167.239us | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 1.000s | 122.839us | 1 | 1 | 100.00 |
| V2 | intr_test | mbx_intr_test | 2.000s | 40.366us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 3.000s | 66.594us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 3.000s | 66.594us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 1.000s | 40.956us | 1 | 1 | 100.00 |
| mbx_csr_rw | 1.000s | 15.705us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 2.000s | 23.812us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 2.000s | 21.199us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 1.000s | 40.956us | 1 | 1 | 100.00 |
| mbx_csr_rw | 1.000s | 15.705us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 2.000s | 23.812us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 2.000s | 21.199us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | mbx_sec_cm | 1.000s | 14.246us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 6.000s | 1901.935us | 1 | 1 | 100.00 | ||
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| TOTAL | 15 | 16 | 93.75 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 93.45 | 96.75 | 92.07 | 96.71 | 89.54 | 86.12 | -- | 96.81 | 85.35 |
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched has 1 failures:
0.mbx_stress.24825216191608076683015622355185616996348218489448079073738519749991933611586
Line 874, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log
UVM_ERROR @ 1901314297 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 643573069 [0x265c254d]) RDATA read data mismatched
UVM_INFO @ 1901314297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---