OTBN Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: `33c2274`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	9.000s	186.802us	1	1	100.00
V1	single_binary	otbn_single	6.000s	19.158us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	3.000s	43.049us	1	1	100.00
V1	csr_rw	otbn_csr_rw	3.000s	43.689us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	5.000s	69.070us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	4.000s	16.079us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	5.000s	79.832us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	3.000s	43.689us	1	1	100.00
		otbn_csr_aliasing	4.000s	16.079us	1	1	100.00
V1	mem_walk	otbn_mem_walk	20.000s	1392.192us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	6.000s	71.032us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	17.000s	258.801us	1	1	100.00
V2	multi_error	otbn_multi_err	45.000s	273.834us	1	1	100.00
V2	back_to_back	otbn_multi	15.000s	54.163us	1	1	100.00
V2	stress_all	otbn_stress_all	31.000s	129.280us	1	1	100.00
V2	lc_escalation	otbn_escalate	5.000s	68.275us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	5.000s	20.855us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	7.000s	82.834us	1	1	100.00
V2	alert_test	otbn_alert_test	4.000s	54.788us	1	1	100.00
V2	intr_test	otbn_intr_test	4.000s	23.837us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	5.000s	130.155us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	5.000s	130.155us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	3.000s	43.049us	1	1	100.00
		otbn_csr_rw	3.000s	43.689us	1	1	100.00
		otbn_csr_aliasing	4.000s	16.079us	1	1	100.00
		otbn_same_csr_outstanding	5.000s	83.064us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	3.000s	43.049us	1	1	100.00
		otbn_csr_rw	3.000s	43.689us	1	1	100.00
		otbn_csr_aliasing	4.000s	16.079us	1	1	100.00
		otbn_same_csr_outstanding	5.000s	83.064us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	7.000s	54.985us	1	1	100.00
		otbn_dmem_err	7.000s	30.039us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	7.000s	105.502us	1	1	100.00
		otbn_controller_ispr_rdata_err	10.000s	67.440us	1	1	100.00
		otbn_mac_bignum_acc_err	7.000s	32.931us	1	1	100.00
		otbn_urnd_err	4.000s	15.738us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	6.000s	21.937us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	5.000s	31.418us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	29.480us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	6.000s	120.042us	0	1	0.00
		otbn_tl_intg_err	15.000s	297.817us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	12.000s	337.468us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.000s	120.042us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	6.000s	120.042us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	9.000s	186.802us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	7.000s	30.039us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	7.000s	54.985us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	15.000s	297.817us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	5.000s	68.275us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	7.000s	54.985us	1	1	100.00
		otbn_dmem_err	7.000s	30.039us	1	1	100.00
		otbn_zero_state_err_urnd	5.000s	20.855us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	21.937us	1	1	100.00
		otbn_sec_cm	6.000s	120.042us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.000s	120.042us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	6.000s	19.158us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	7.000s	54.985us	1	1	100.00
		otbn_dmem_err	7.000s	30.039us	1	1	100.00
		otbn_zero_state_err_urnd	5.000s	20.855us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	21.937us	1	1	100.00
		otbn_sec_cm	6.000s	120.042us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.000s	120.042us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	5.000s	68.275us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	7.000s	54.985us	1	1	100.00
		otbn_dmem_err	7.000s	30.039us	1	1	100.00
		otbn_zero_state_err_urnd	5.000s	20.855us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	21.937us	1	1	100.00
		otbn_sec_cm	6.000s	120.042us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.000s	120.042us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	6.000s	19.158us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	7.000s	27.436us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	6.000s	21.438us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	43.000s	1006.619us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	43.000s	1006.619us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	6.000s	14.806us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.000s	120.042us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.000s	120.042us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	5.000s	228.079us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.000s	120.042us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.000s	120.042us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	7.000s	25.528us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	7.000s	25.528us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	5.000s	15.214us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	6.000s	19.158us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	6.000s	19.158us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	6.000s	19.158us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	15.000s	54.163us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	6.000s	19.158us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	6.000s	19.158us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	16.000s	224.892us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	6.000s	19.158us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.000s	120.042us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	21.000s	481.375us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	41	92.68

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.64	99.46	93.52	99.57	90.45	91.62	94.87	87.01	94.44

Failure Buckets

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.73305341472742922919676272709482743429293396923971637032728345291542977471771
    Line 182, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 481375331 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 481375331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 0.otbn_sec_wipe_err.101345582229322141061727718847033435541461723328349602772869784733105398280573
    Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 15213587 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  15213587 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  15213587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

0.otbn_sec_cm.85938553947402958756390707908404484148089970562935482064508748219419809279491
Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 120041982 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 120041982 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 120041982 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 120041982 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 120041982 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed