PRIM_ESC Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	prim_esc_request_test	prim_esc_test	0.410s	0.000us	1	1	100.00
V1	prim_ping_req_interrupted_by_esc_req_test	prim_esc_test	0.410s	0.000us	1	1	100.00
V1	prim_esc_tx_integrity_errors_test	prim_esc_test	0.410s	0.000us	1	1	100.00
V1	prim_esc_reverse_ping_timeout_test	prim_esc_test	0.410s	0.000us	1	1	100.00
V1	prim_esc_receiver_counter_fail_test	prim_esc_test	0.410s	0.000us	1	1	100.00
V1	prim_esc_handshake_with_rand_reset_test	prim_esc_test	0.410s	0.000us	1	1	100.00
V1		TOTAL			1	1	100.00
		TOTAL			1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.47	90.83	85.37	100.00	71.43	80.00	85.19