ROM_CTRL/64KB Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.920s	0.000us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.070s	0.000us	2	2	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.300s	0.000us	2	2	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.390s	0.000us	2	2	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.960s	0.000us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.970s	0.000us	2	2	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.300s	0.000us	2	2	100.00
		rom_ctrl_csr_aliasing	6.960s	0.000us	2	2	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.150s	0.000us	2	2	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.540s	0.000us	2	2	100.00
V1		TOTAL			16	16	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	10.250s	0.000us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	22.850s	0.000us	2	2	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	13.510s	0.000us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	6.160s	0.000us	2	2	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	14.110s	0.000us	2	2	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	14.110s	0.000us	2	2	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.070s	0.000us	2	2	100.00
		rom_ctrl_csr_rw	7.300s	0.000us	2	2	100.00
		rom_ctrl_csr_aliasing	6.960s	0.000us	2	2	100.00
		rom_ctrl_same_csr_outstanding	9.620s	0.000us	2	2	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.070s	0.000us	2	2	100.00
		rom_ctrl_csr_rw	7.300s	0.000us	2	2	100.00
		rom_ctrl_csr_aliasing	6.960s	0.000us	2	2	100.00
		rom_ctrl_same_csr_outstanding	9.620s	0.000us	2	2	100.00
V2		TOTAL			12	12	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	141.190s	0.000us	2	2	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	39.360s	0.000us	2	2	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	248.180s	0.000us	1	2	50.00
		rom_ctrl_tl_intg_err	51.780s	0.000us	2	2	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	248.180s	0.000us	1	2	50.00
V2S	prim_count_check	rom_ctrl_sec_cm	248.180s	0.000us	1	2	50.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	141.190s	0.000us	2	2	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	141.190s	0.000us	2	2	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	141.190s	0.000us	2	2	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	141.190s	0.000us	2	2	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	141.190s	0.000us	2	2	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	248.180s	0.000us	1	2	50.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	248.180s	0.000us	1	2	50.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.920s	0.000us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.920s	0.000us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.920s	0.000us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	51.780s	0.000us	2	2	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	141.190s	0.000us	2	2	100.00
		rom_ctrl_kmac_err_chk	13.510s	0.000us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	141.190s	0.000us	2	2	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	141.190s	0.000us	2	2	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	141.190s	0.000us	2	2	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	39.360s	0.000us	2	2	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	248.180s	0.000us	1	2	50.00
V2S		TOTAL			7	8	87.50
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	362.150s	0.000us	2	2	100.00
V3		TOTAL			2	2	100.00
		TOTAL			37	38	97.37

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.68	99.59	98.22	100.00	100.00	99.27	96.80	96.90

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.21127328648930557248398434319935183611660248407859573048530413974464776344351
      Line 167, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 8598354ps failed at 8598354ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 10367085ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 10367085ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))