RV_TIMER Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.730s	0.000us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.640s	0.000us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.680s	0.000us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.240s	0.000us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.600s	0.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.060s	0.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.680s	0.000us	1	1	100.00
		rv_timer_csr_aliasing	0.600s	0.000us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.970s	0.000us	0	1	0.00
V2	disabled	rv_timer_disabled	0.690s	0.000us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	780.120s	0.000us	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	780.120s	0.000us	1	1	100.00
V2	stress	rv_timer_stress_all	0.680s	0.000us	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.660s	0.000us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.700s	0.000us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.910s	0.000us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.910s	0.000us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.640s	0.000us	1	1	100.00
		rv_timer_csr_rw	0.680s	0.000us	1	1	100.00
		rv_timer_csr_aliasing	0.600s	0.000us	1	1	100.00
		rv_timer_same_csr_outstanding	0.620s	0.000us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.640s	0.000us	1	1	100.00
		rv_timer_csr_rw	0.680s	0.000us	1	1	100.00
		rv_timer_csr_aliasing	0.600s	0.000us	1	1	100.00
		rv_timer_same_csr_outstanding	0.620s	0.000us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.950s	0.000us	1	1	100.00
		rv_timer_tl_intg_err	1.100s	0.000us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.100s	0.000us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.730s	0.000us	0	1	0.00
V3	max_value	rv_timer_max	0.740s	0.000us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	11.550s	0.000us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			15	19	78.95

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.18	100.00	99.69	100.00	--	100.00	96.82	80.59

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.85815152657591468763389730762364684210404760847160685784840539294536477966509
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 220833441 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x46f5df04) == 0x1
        UVM_INFO @ 220833441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.92305715311023866471145999642120160114530705588092141730628860575840964442488
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 2296824629 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe96ef904) == 0x1
        UVM_INFO @ 2296824629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.73926773687664013846592539546661097616341825829498093996673604890545986227734
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 472561319 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 472561319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:

  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.39689960440545359667107801857167641686939493136685937558182824072160842071107
      Line 208, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 3589775519 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
        UVM_INFO @ 3589775519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---