SPI_DEVICE/1R1W Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	458.120s	0.000us	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.550s	0.000us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.510s	0.000us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	12.840s	0.000us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.870s	0.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.020s	0.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.510s	0.000us	1	1	100.00
		spi_device_csr_aliasing	5.870s	0.000us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.780s	0.000us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.310s	0.000us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.060s	0.000us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.900s	0.000us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.880s	0.000us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.190s	0.000us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.190s	0.000us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.240s	0.000us	1	1	100.00
		spi_device_tpm_sts_read	0.850s	0.000us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	18.910s	0.000us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.170s	0.000us	1	1	100.00
		spi_device_flash_all	86.410s	0.000us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	6.030s	0.000us	1	1	100.00
		spi_device_flash_all	86.410s	0.000us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	6.030s	0.000us	1	1	100.00
		spi_device_flash_all	86.410s	0.000us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	86.410s	0.000us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.800s	0.000us	1	1	100.00
		spi_device_flash_all	86.410s	0.000us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.800s	0.000us	1	1	100.00
		spi_device_flash_all	86.410s	0.000us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.800s	0.000us	1	1	100.00
		spi_device_flash_all	86.410s	0.000us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.800s	0.000us	1	1	100.00
		spi_device_flash_all	86.410s	0.000us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.800s	0.000us	1	1	100.00
		spi_device_flash_all	86.410s	0.000us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.090s	0.000us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	5.170s	0.000us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	5.170s	0.000us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	5.170s	0.000us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	5.670s	0.000us	1	1	100.00
		spi_device_read_buffer_direct	2.780s	0.000us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	5.170s	0.000us	1	1	100.00
		spi_device_flash_all	86.410s	0.000us	1	1	100.00
V2	quad_spi	spi_device_flash_all	86.410s	0.000us	1	1	100.00
V2	dual_spi	spi_device_flash_all	86.410s	0.000us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	10.050s	0.000us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	10.050s	0.000us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	458.120s	0.000us	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	42.870s	0.000us	1	1	100.00
V2	stress_all	spi_device_stress_all	28.030s	0.000us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.850s	0.000us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.880s	0.000us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.350s	0.000us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.350s	0.000us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.550s	0.000us	1	1	100.00
		spi_device_csr_rw	2.510s	0.000us	1	1	100.00
		spi_device_csr_aliasing	5.870s	0.000us	1	1	100.00
		spi_device_same_csr_outstanding	2.600s	0.000us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.550s	0.000us	1	1	100.00
		spi_device_csr_rw	2.510s	0.000us	1	1	100.00
		spi_device_csr_aliasing	5.870s	0.000us	1	1	100.00
		spi_device_same_csr_outstanding	2.600s	0.000us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_tl_intg_err	13.540s	0.000us	1	1	100.00
		spi_device_sec_cm	1.070s	0.000us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	13.540s	0.000us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	30.250s	0.000us	1	1	100.00
		TOTAL			31	33	93.94

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.14	99.05	96.00	83.01	89.36	98.25	94.30	71.03

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.113609332787246460995700841611787117135337842725175671723753393043871463300667
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1964838 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[72])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1964838 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1964838 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[968])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.105805479203167500094315662122198968842020589986531972487257226903187768817411
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1105396 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6cee95 [11011001110111010010101] vs 0x0 [0])
        UVM_ERROR @   1117396 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x636bee [11000110110101111101110] vs 0x0 [0])
        UVM_ERROR @   1169396 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5d8524 [10111011000010100100100] vs 0x0 [0])
        UVM_ERROR @   1176396 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc36107 [110000110110000100000111] vs 0x0 [0])
        UVM_ERROR @   1274396 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x540723 [10101000000011100100011] vs 0x0 [0])