SPI_HOST Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	29.000s	908.695us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	17.889us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	16.569us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	37.756us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	68.289us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	82.692us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	16.569us	1	1	100.00
		spi_host_csr_aliasing	1.000s	68.289us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	31.203us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	94.234us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	1.000s	36.954us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	51.114us	1	1	100.00
		spi_host_error_cmd	1.000s	188.775us	1	1	100.00
		spi_host_event	9.000s	3851.016us	1	1	100.00
V2	clock_rate	spi_host_speed	3.000s	169.470us	1	1	100.00
V2	speed	spi_host_speed	3.000s	169.470us	1	1	100.00
V2	chip_select_timing	spi_host_speed	3.000s	169.470us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	195.308us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	64.693us	1	1	100.00
V2	cpol_cpha	spi_host_speed	3.000s	169.470us	1	1	100.00
V2	full_cycle	spi_host_speed	3.000s	169.470us	1	1	100.00
V2	duplex	spi_host_smoke	29.000s	908.695us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	29.000s	908.695us	1	1	100.00
V2	stress_all	spi_host_stress_all	16.000s	1849.206us	1	1	100.00
V2	spien	spi_host_spien	7.000s	1324.019us	1	1	100.00
V2	stall	spi_host_status_stall	9.000s	627.209us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	2213.744us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	51.114us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	16.708us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	21.426us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	57.235us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	57.235us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	17.889us	1	1	100.00
		spi_host_csr_rw	1.000s	16.569us	1	1	100.00
		spi_host_csr_aliasing	1.000s	68.289us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	39.198us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	17.889us	1	1	100.00
		spi_host_csr_rw	1.000s	16.569us	1	1	100.00
		spi_host_csr_aliasing	1.000s	68.289us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	39.198us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_sec_cm	1.000s	236.217us	1	1	100.00
		spi_host_tl_intg_err	2.000s	175.403us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	175.403us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	387.000s	12461.995us	1	1	100.00
		TOTAL			26	26	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.75	96.82	93.35	98.69	91.58	88.02	100.00	94.38	87.92