SRAM_CTRL/MAIN Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	65.910s	0.000us	2	2	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	0.000us	2	2	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.820s	0.000us	2	2	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.330s	0.000us	2	2	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.830s	0.000us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.180s	0.000us	1	2	50.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.820s	0.000us	2	2	100.00
		sram_ctrl_csr_aliasing	0.830s	0.000us	2	2	100.00
V1	mem_walk	sram_ctrl_mem_walk	256.910s	0.000us	2	2	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	69.080s	0.000us	2	2	100.00
V1		TOTAL			15	16	93.75
V2	multiple_keys	sram_ctrl_multiple_keys	696.860s	0.000us	2	2	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	225.140s	0.000us	2	2	100.00
V2	bijection	sram_ctrl_bijection	429.290s	0.000us	2	2	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	684.630s	0.000us	2	2	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	26.560s	0.000us	2	2	100.00
V2	executable	sram_ctrl_executable	384.130s	0.000us	2	2	100.00
V2	partial_access	sram_ctrl_partial_access	14.830s	0.000us	2	2	100.00
		sram_ctrl_partial_access_b2b	387.780s	0.000us	2	2	100.00
V2	max_throughput	sram_ctrl_max_throughput	36.100s	0.000us	2	2	100.00
		sram_ctrl_throughput_w_partial_write	34.300s	0.000us	2	2	100.00
		sram_ctrl_throughput_w_readback	58.020s	0.000us	2	2	100.00
V2	regwen	sram_ctrl_regwen	627.660s	0.000us	2	2	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.640s	0.000us	2	2	100.00
V2	stress_all	sram_ctrl_stress_all	2346.300s	0.000us	2	2	100.00
V2	alert_test	sram_ctrl_alert_test	0.860s	0.000us	2	2	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.110s	0.000us	2	2	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.110s	0.000us	2	2	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	0.000us	2	2	100.00
		sram_ctrl_csr_rw	0.820s	0.000us	2	2	100.00
		sram_ctrl_csr_aliasing	0.830s	0.000us	2	2	100.00
		sram_ctrl_same_csr_outstanding	0.760s	0.000us	2	2	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	0.000us	2	2	100.00
		sram_ctrl_csr_rw	0.820s	0.000us	2	2	100.00
		sram_ctrl_csr_aliasing	0.830s	0.000us	2	2	100.00
		sram_ctrl_same_csr_outstanding	0.760s	0.000us	2	2	100.00
V2		TOTAL			34	34	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	34.010s	0.000us	2	2	100.00
V2S	tl_intg_err	sram_ctrl_tl_intg_err	1.990s	0.000us	2	2	100.00
		sram_ctrl_sec_cm	0.900s	0.000us	0	2	0.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.900s	0.000us	0	2	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.990s	0.000us	2	2	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	627.660s	0.000us	2	2	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	627.660s	0.000us	2	2	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.820s	0.000us	2	2	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	384.130s	0.000us	2	2	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	384.130s	0.000us	2	2	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	384.130s	0.000us	2	2	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	26.560s	0.000us	2	2	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.620s	0.000us	2	2	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	34.010s	0.000us	2	2	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.980s	0.000us	0	2	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	65.910s	0.000us	2	2	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	65.910s	0.000us	2	2	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	384.130s	0.000us	2	2	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.900s	0.000us	0	2	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	26.560s	0.000us	2	2	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.900s	0.000us	0	2	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.900s	0.000us	0	2	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	65.910s	0.000us	2	2	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.900s	0.000us	0	2	0.00
V2S		TOTAL			6	10	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	193.210s	0.000us	2	2	100.00
V3		TOTAL			2	2	100.00
		TOTAL			57	62	91.94

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.56	98.84	91.55	90.71	100.00	96.53	95.55	95.73

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 2 failures:

  • Test sram_ctrl_readback_err has 2 failures.

    • 0.sram_ctrl_readback_err.103250526113016093683170957636598511910228370531268560035428854745662469321370
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  45819351 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x46) != exp (0x42)
        UVM_INFO @  45819351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.sram_ctrl_readback_err.15735172127340044093527041234103417707749839103627656109474197853879795908597
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2628798457 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6f) != exp (0x25)
        UVM_INFO @ 2628798457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.65114175565786249912669080979272518023097163400111701326259292655119109213779
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 109389519 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
        UVM_INFO @ 109389519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.77406876622890444052301945720535425081545783295722400272017489054291588285307
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  11983274 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  11983274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.5534054563092611205697865352580213323509496558618306189912500723236188508709
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   4856958 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   4856958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---