UART Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: 33c2274

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	3.540s	0.000us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.580s	0.000us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.630s	0.000us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.620s	0.000us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.590s	0.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.780s	0.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.630s	0.000us	1	1	100.00
		uart_csr_aliasing	0.590s	0.000us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	3.430s	0.000us	1	1	100.00
V2	parity	uart_smoke	3.540s	0.000us	1	1	100.00
		uart_tx_rx	3.430s	0.000us	1	1	100.00
V2	parity_error	uart_intr	4.500s	0.000us	1	1	100.00
		uart_rx_parity_err	44.030s	0.000us	1	1	100.00
V2	watermark	uart_tx_rx	3.430s	0.000us	1	1	100.00
		uart_intr	4.500s	0.000us	1	1	100.00
V2	fifo_full	uart_fifo_full	24.010s	0.000us	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	46.330s	0.000us	1	1	100.00
V2	fifo_reset	uart_fifo_reset	71.870s	0.000us	1	1	100.00
V2	rx_frame_err	uart_intr	4.500s	0.000us	1	1	100.00
V2	rx_break_err	uart_intr	4.500s	0.000us	1	1	100.00
V2	rx_timeout	uart_intr	4.500s	0.000us	1	1	100.00
V2	perf	uart_perf	168.010s	0.000us	1	1	100.00
V2	sys_loopback	uart_loopback	2.200s	0.000us	1	1	100.00
V2	line_loopback	uart_loopback	2.200s	0.000us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	4.780s	0.000us	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	0.780s	0.000us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.840s	0.000us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	9.880s	0.000us	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	500.500s	0.000us	1	1	100.00
V2	stress_all	uart_stress_all	39.280s	0.000us	0	1	0.00
V2	alert_test	uart_alert_test	0.570s	0.000us	1	1	100.00
V2	intr_test	uart_intr_test	0.600s	0.000us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.480s	0.000us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.480s	0.000us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.580s	0.000us	1	1	100.00
		uart_csr_rw	0.630s	0.000us	1	1	100.00
		uart_csr_aliasing	0.590s	0.000us	1	1	100.00
		uart_same_csr_outstanding	0.700s	0.000us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.580s	0.000us	1	1	100.00
		uart_csr_rw	0.630s	0.000us	1	1	100.00
		uart_csr_aliasing	0.590s	0.000us	1	1	100.00
		uart_same_csr_outstanding	0.700s	0.000us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	0.760s	0.000us	1	1	100.00
		uart_tl_intg_err	1.090s	0.000us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.090s	0.000us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	12.760s	0.000us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.50	98.86	92.65	91.55	--	96.27	97.12	42.55

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 2 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.32281971983211653986557589789439163050922212199768092212708144173383185772217
      Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 11181542642 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5,                                 clk_pulses: 0
        UVM_ERROR @ 11181584309 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 11181875978 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (213 [0xd5] vs 191 [0xbf]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 11181917645 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 11182292648 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (213 [0xd5] vs 239 [0xef]) reg name: uart_reg_block.rdata
      

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.73035279774666341103005110409558586951581961317546806551219073694023522770877
      Line 101, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 60792861284 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 60792884540 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 60793024076 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (156 [0x9c] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 60793047332 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 60793070588 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (156 [0x9c] vs 254 [0xfe]) reg name: uart_reg_block.rdata