CHIP Simulation Results

Thursday November 13 2025 16:09:11 UTC

GitHub Revision: `33c2274`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	66.431s	0.000us	0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	66.431s	0.000us	0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	32.401s	0.000us	0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	18.839s	0.000us	0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	300.230s	0.000us	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	300.230s	0.000us	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	300.230s	0.000us	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	30.260s	0.000us	0	1	0.00
		chip_sw_example_manufacturer	139.842s	0.000us	0	1	0.00
		chip_sw_example_concurrency	171.910s	0.000us	1	1	100.00
		chip_sw_uart_smoketest_signed	9.851s	0.000us	0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.460s	0.000us	0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.210s	0.000us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.210s	0.000us	0	1	0.00
V1	xbar_smoke	xbar_smoke	21.980s	0.000us	1	1	100.00
V1		TOTAL			3	11	27.27
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	51.473s	0.000us	0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	1751.570s	0.000us	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	275.060s	0.000us	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	19.954s	0.000us	0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	28.302s	0.000us	0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	14.281s	0.000us	0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	40.799s	0.000us	0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	2.750s	0.000us	0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.750s	0.000us	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	85.752s	0.000us	0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	77.269s	0.000us	0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	96.462s	0.000us	0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	96.462s	0.000us	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	121.390s	0.000us	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	110.790s	0.000us	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	243.070s	0.000us	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.126s	0.000us	0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.638s	0.000us	0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	821.050s	0.000us	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	229.650s	0.000us	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	485.590s	0.000us	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	485.590s	0.000us	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.836s	0.000us	0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	202.970s	0.000us	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	202.970s	0.000us	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	283.020s	0.000us	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	167.290s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	273.930s	0.000us	1	1	100.00
		chip_sw_aes_idle	164.280s	0.000us	1	1	100.00
		chip_sw_hmac_enc_idle	172.910s	0.000us	1	1	100.00
		chip_sw_kmac_idle	160.920s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	166.010s	0.000us	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	177.440s	0.000us	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	182.000s	0.000us	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	169.060s	0.000us	0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	35.940s	0.000us	0	1	0.00
		chip_sw_aes_enc_jitter_en	43.400s	0.000us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.090s	0.000us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.020s	0.000us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	40.960s	0.000us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.776s	0.000us	0	1	0.00
		chip_sw_clkmgr_jitter	143.760s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	315.390s	0.000us	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	37.530s	0.000us	0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	37.150s	0.000us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	37.240s	0.000us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	38.030s	0.000us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	38.540s	0.000us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	38.800s	0.000us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.142s	0.000us	0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.843s	0.000us	0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.201s	0.000us	0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	10.360s	0.000us	0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	949.180s	0.000us	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	359.440s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	202.970s	0.000us	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.429s	0.000us	0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	359.440s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	10.085s	0.000us	0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	11.958s	0.000us	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.717s	0.000us	0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.957s	0.000us	0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.602s	0.000us	0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	949.180s	0.000us	0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	243.070s	0.000us	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	327.200s	0.000us	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	280.570s	0.000us	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	278.770s	0.000us	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	159.110s	0.000us	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	949.180s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.352s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.661s	0.000us	0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	949.180s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.778s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	278.770s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.207s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.202s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.137s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.574s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	9.605s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9.413s	0.000us	0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.661s	0.000us	0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	11.516s	0.000us	0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	18.357s	0.000us	0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.516s	0.000us	0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.516s	0.000us	0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.516s	0.000us	0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	272.540s	0.000us	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_prim_tl_access	96.080s	0.000us	1	1	100.00
		chip_rv_dm_lc_disabled	821.050s	0.000us	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	26.196s	0.000us	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	20.939s	0.000us	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	24.555s	0.000us	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.524s	0.000us	0	1	0.00
		chip_sw_lc_ctrl_transition	11.516s	0.000us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	268.860s	0.000us	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	761.910s	0.000us	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.236s	0.000us	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	184.230s	0.000us	1	1	100.00
		chip_sw_aes_enc_jitter_en	43.400s	0.000us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	153.490s	0.000us	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	164.280s	0.000us	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	170.880s	0.000us	1	1	100.00
		chip_sw_hmac_enc_jitter_en	36.090s	0.000us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	172.910s	0.000us	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	149.100s	0.000us	1	1	100.00
		chip_sw_kmac_mode_kmac	205.470s	0.000us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	40.960s	0.000us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	268.860s	0.000us	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.516s	0.000us	0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	32.950s	0.000us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	254.610s	0.000us	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	160.920s	0.000us	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	390.620s	0.000us	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	390.620s	0.000us	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.342s	0.000us	0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	170.170s	0.000us	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.556s	0.000us	0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	268.860s	0.000us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.020s	0.000us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	2322.460s	0.000us	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	35.940s	0.000us	0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	273.930s	0.000us	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	273.930s	0.000us	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	273.930s	0.000us	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	362.580s	0.000us	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	761.910s	0.000us	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	761.910s	0.000us	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	326.900s	0.000us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.776s	0.000us	0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.236s	0.000us	0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	949.180s	0.000us	0	1	0.00
		chip_sw_data_integrity_escalation	96.462s	0.000us	0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.516s	0.000us	0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	362.580s	0.000us	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	268.860s	0.000us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	326.900s	0.000us	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	174.930s	0.000us	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	362.580s	0.000us	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	268.860s	0.000us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	326.900s	0.000us	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	174.930s	0.000us	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.516s	0.000us	0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	9.242s	0.000us	0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	18.357s	0.000us	0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_prim_tl_access	96.080s	0.000us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	26.196s	0.000us	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	20.939s	0.000us	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	24.555s	0.000us	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.524s	0.000us	0	1	0.00
		chip_sw_lc_ctrl_transition	11.516s	0.000us	0	1	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	96.080s	0.000us	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	9.740s	0.000us	0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	16.496s	0.000us	0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.843s	0.000us	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	35.940s	0.000us	0	1	0.00
		chip_sw_aes_enc_jitter_en	43.400s	0.000us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.090s	0.000us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.020s	0.000us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	40.960s	0.000us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.776s	0.000us	0	1	0.00
		chip_sw_clkmgr_jitter	143.760s	0.000us	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	162.460s	0.000us	0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	162.460s	0.000us	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	176.120s	0.000us	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	156.180s	0.000us	0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	376.100s	0.000us	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	225.110s	0.000us	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	176.270s	0.000us	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	174.930s	0.000us	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	327.200s	0.000us	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	327.200s	0.000us	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	150.670s	0.000us	1	1	100.00
		chip_sw_aon_timer_smoketest	147.040s	0.000us	1	1	100.00
		chip_sw_clkmgr_smoketest	124.450s	0.000us	1	1	100.00
		chip_sw_csrng_smoketest	124.030s	0.000us	1	1	100.00
		chip_sw_gpio_smoketest	142.700s	0.000us	1	1	100.00
		chip_sw_hmac_smoketest	175.010s	0.000us	1	1	100.00
		chip_sw_kmac_smoketest	158.200s	0.000us	1	1	100.00
		chip_sw_otbn_smoketest	190.410s	0.000us	1	1	100.00
		chip_sw_otp_ctrl_smoketest	127.950s	0.000us	1	1	100.00
		chip_sw_rv_plic_smoketest	126.860s	0.000us	1	1	100.00
		chip_sw_rv_timer_smoketest	183.450s	0.000us	1	1	100.00
		chip_sw_rstmgr_smoketest	119.080s	0.000us	1	1	100.00
		chip_sw_sram_ctrl_smoketest	128.740s	0.000us	1	1	100.00
		chip_sw_uart_smoketest	135.720s	0.000us	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	9.385s	0.000us	0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	9.851s	0.000us	0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	51.473s	0.000us	0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.651s	0.000us	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	234.360s	0.000us	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	194.190s	0.000us	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	174.890s	0.000us	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	173.960s	0.000us	1	1	100.00
V2	chip_lc_test_locked	chip_rv_dm_lc_disabled	821.050s	0.000us	0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	9.800s	0.000us	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	9.825s	0.000us	0	1	0.00
		chip_sw_lc_walkthrough_prod	11.806s	0.000us	0	1	0.00
		chip_sw_lc_walkthrough_prodend	22.554s	0.000us	0	1	0.00
		chip_sw_lc_walkthrough_rma	21.182s	0.000us	0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	9.800s	0.000us	0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	561.270s	0.000us	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	468.070s	0.000us	1	1	100.00
		rom_volatile_raw_unlock	9.692s	0.000us	0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.953s	0.000us	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	44.905s	0.000us	0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	44.860s	0.000us	0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	119.710s	0.000us	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	119.710s	0.000us	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.210s	0.000us	0	1	0.00
		chip_same_csr_outstanding	8.480s	0.000us	0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.210s	0.000us	0	1	0.00
		chip_same_csr_outstanding	8.480s	0.000us	0	1	0.00
V2	xbar_base_random_sequence	xbar_random	109.930s	0.000us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.150s	0.000us	1	1	100.00
		xbar_smoke_large_delays	293.640s	0.000us	1	1	100.00
		xbar_smoke_slow_rsp	326.680s	0.000us	1	1	100.00
		xbar_random_zero_delays	30.490s	0.000us	1	1	100.00
		xbar_random_large_delays	1096.420s	0.000us	1	1	100.00
		xbar_random_slow_rsp	930.740s	0.000us	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	150.810s	0.000us	1	1	100.00
		xbar_error_and_unmapped_addr	9.660s	0.000us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	14.680s	0.000us	1	1	100.00
		xbar_error_and_unmapped_addr	9.660s	0.000us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	333.750s	0.000us	1	1	100.00
		xbar_access_same_device_slow_rsp	804.710s	0.000us	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	124.140s	0.000us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	174.350s	0.000us	1	1	100.00
		xbar_stress_all_with_error	55.670s	0.000us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1436.620s	0.000us	1	1	100.00
		xbar_stress_all_with_reset_error	1824.990s	0.000us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	10.632s	0.000us	0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.240s	0.000us	0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.625s	0.000us	0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.388s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.237s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.657s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.319s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	9.721s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.207s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.463s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	9.976s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	9.372s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.216s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	61.642s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	78.796s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	67.782s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	69.888s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	79.772s	0.000us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	74.984s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	59.447s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	68.073s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	66.071s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	52.904s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	64.454s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	52.543s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	64.174s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	60.737s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	61.247s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	26.301s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	29.829s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	9.984s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	15.845s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	10.713s	0.000us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	10.890s	0.000us	0	1	0.00
		rom_e2e_asm_init_dev	10.272s	0.000us	0	1	0.00
		rom_e2e_asm_init_prod	9.801s	0.000us	0	1	0.00
		rom_e2e_asm_init_prod_end	13.322s	0.000us	0	1	0.00
		rom_e2e_asm_init_rma	9.832s	0.000us	0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	9.462s	0.000us	0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	9.055s	0.000us	0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	9.959s	0.000us	0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	9.495s	0.000us	0	1	0.00
V2		TOTAL			67	197	34.01
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	191.790s	0.000us	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	156.970s	0.000us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	9.255s	0.000us	0	1	0.00
		rom_e2e_jtag_debug_dev	11.588s	0.000us	0	1	0.00
		rom_e2e_jtag_debug_rma	9.328s	0.000us	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.066s	0.000us	0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	949.180s	0.000us	0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	10.818s	0.000us	0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	198.990s	0.000us	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	9.737s	0.000us	0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	9.454s	0.000us	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	9.255s	0.000us	0	1	0.00
		rom_e2e_jtag_debug_dev	11.588s	0.000us	0	1	0.00
		rom_e2e_jtag_debug_rma	9.328s	0.000us	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	13.343s	0.000us	0	1	0.00
		rom_e2e_jtag_inject_dev	11.335s	0.000us	0	1	0.00
		rom_e2e_jtag_inject_rma	9.657s	0.000us	0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.084s	0.000us	0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	922.450s	0.000us	0	1	0.00
		chip_sw_entropy_src_kat_test	160.420s	0.000us	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	147.570s	0.000us	1	1	100.00
		chip_plic_all_irqs_0	432.080s	0.000us	1	1	100.00
		chip_plic_all_irqs_10	329.540s	0.000us	1	1	100.00
		chip_sw_dma_inline_hashing	178.060s	0.000us	1	1	100.00
		chip_sw_dma_abort	189.900s	0.000us	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.969s	0.000us	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.942s	0.000us	0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	9.732s	0.000us	0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	9.551s	0.000us	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	9.200s	0.000us	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	9.348s	0.000us	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	9.196s	0.000us	0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	9.803s	0.000us	0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	9.547s	0.000us	0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	9.445s	0.000us	0	1	0.00
		chip_sw_entropy_src_smoketest	165.030s	0.000us	1	1	100.00
		chip_sw_mbx_smoketest	367.080s	0.000us	1	1	100.00
		TOTAL			79	241	32.78

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
67.81	71.84	71.49	62.31	57.14	77.33	68.05	66.48

Failure Buckets

Job returned non-zero exit code has 122 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.28203341215375905144563860421761209592891078108822526748650221042617259917294
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 129.699s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.39698305620018302109522808461527832454878118666467885139616476823373952830429
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 87.658s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.19148812236317308873679657743790864676590746486981212656609080544756416196518
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 77.084s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.56419048042277298448057639536001149354203511753236370826205808806784386924156
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 65.666s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.85220998145310703254475821799995905845259708860762117719113059710380680584731
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 54.732s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 117 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 11 failures:
- Test chip_sw_otbn_ecdsa_op_irq_jitter_en has 1 failures.
  - 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.106944582925265033679882336182629866687661593622350609382039506238825627384385
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.71001622882040625041002524185377968837010282624584896838229946346906485159876
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.1256670560741497375625318660976994382697605556114588140529788932153113277822
    Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.11445906670010597360434661586957442010956963947525392691699864414891394867681
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.6110120873539843647407744667102274843498225432726185774548244952475540922295
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 6 failures:
- Test chip_sw_rstmgr_cpu_info has 1 failures.
  - 0.chip_sw_rstmgr_cpu_info.5720222264898713440878378375604998566525743392774611286961754103074263210966
    Line 416, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 375.264000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 375.264000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_soc_proxy_smoketest has 1 failures.
  - 0.chip_sw_soc_proxy_smoketest.27654851499116479310691124824448503658903919514646830987328039588089852819550
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
```
      Offending '((!rstreqs[1]) && (reset_cause != HwReq))'
  UVM_ERROR @ 143.536000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 143.536000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_aes_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_aes_trans.96994889460420829680306054513576244355769125353681995705269679040603152033914
    Line 408, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.600000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.600000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_hmac_trans.87507837996973173955084183407129826253262362074479506709971305487315075248152
    Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_kmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_kmac_trans.92516933454769093422193336970144533573953022514330377020113462263256933058803
    Line 406, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.680000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.680000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 1 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.32831343528786064898694448688015916384795534977199511692390845128963178203063
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.23989098579779076920177181996656398822369655478731110989118256818680085897538
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.37622414999233183682592829081651302509335968176091521773497131386059624017308
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 2 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.55465777385216078923196139865086666690325822483054323330595289431711308475409
    Line 457, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 905.666000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
  UVM_INFO @ 905.666000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.
  - 0.chip_sw_rstmgr_rst_cnsty_escalation.45708998004084634891299816275595377281919448187167253789742993571876860746571
    Line 453, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
```
  UVM_ERROR @ 905.666000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
  UVM_INFO @ 905.666000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.18041906349341385938965242814736496306963094589749044426074115389849954240130
Line 407, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 268.020000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (519212121077059159392431086137071521297044317612464208875942330418176455538914517535091847556853501434898789928195229702559306632408953142082242443828316 [0x9e9db21aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd38fbf6bd07f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 268.020000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.23237533674255408384580211913672574457464929764406510152705724321431857275013
Line 407, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 268.332000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (10562457084723821564567977431593510526704242567665068990241006961374875590624044400607792983251044576793367560987002777991228058609399765905460060456574044 [0xc9ac36fbaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd34ffa860a7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 268.332000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42094) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.106303325262601718188886249335283679512451838849543923971934257154864251569411
Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 117.016000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42094) { a_addr: 'h30480000  a_data: 'hca9248e7  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h1  a_user: 'h248da  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 117.016000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.35587632987170685261651278459742773334845848722629644770685417963709584218254
Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 117.019000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42094) { a_addr: 'h30480000  a_data: 'h1f9cd5b6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3e  a_opcode: 'h0  a_user: 'h2692d  d_param: 'h0  d_source: 'h3e  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 117.019000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.115107279339687581296864960325852800030677053370400387695582871052524459441511
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 117.984000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 117.984000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.88326626871921033456444975615769323434398818014052748749888697280612973888358
    Line 288, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 1282.666000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40710 read out mismatch
  UVM_INFO @ 1282.666000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.25669080028177467517518941194296777650780539033075465370609634537153163664560
    Line 574, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.90281575767075867041197700992380884205400876429111044915796544247140062617566
    Line 446, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 298.364000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 298.364000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.90887925958223098439966456271939606953903251696173055974169914621032295035793
    Line 414, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 158.200000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 158.200000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.111052185182128580820187108578033191919379104832260611233023817237057639480833
    Line 417, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 290.282000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
  UVM_INFO @ 290.282000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.44802697980495637074582710407449612353451504169881012625563442882105290665645
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 138.783000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 138.783000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns * has 1 failures:
- Test chip_sw_soc_proxy_gpios has 1 failures.
  - 0.chip_sw_soc_proxy_gpios.98728656290891741281687266593218529747021196131167515141579679268154956569533
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log
```
  UVM_ERROR @ 136.462000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
  UVM_INFO @ 136.462000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 1 failures:
- Test chip_sw_aon_timer_irq has 1 failures.
  - 0.chip_sw_aon_timer_irq.70471615687247624694712463192913994942218755708979873493049285361956154797226
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
```
  UVM_ERROR @ 545.501000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4043 usec which is not in the range 369 usec and 422 usec
  UVM_INFO @ 545.501000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.113076780979133847977973883598289363408445245654375323494713065029147574161493
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 164.305000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 164.305000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.32743702345947760693775519457732068400525236078032995733529322659178214841343
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 251.563000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 251.563000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.37185419952582497911623628796799454638136787845211016846341331546912006969842
    Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == * has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.93212036159802620345160531800132369128940238578188687974491347822049510913550
    Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_ERROR @ 192.913000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
  UVM_INFO @ 192.913000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.13999730779238842141595627285492624332253424131058483905428237248965325019251
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```