Simulation Results: clkmgr

 
18/11/2025 16:10:04 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 71.33
  • line
  • 81.84
  • cond
  • 78.95
  • toggle
  • 96.51
  • fsm
  • 0.0
  • branch
  • 86.59
  • assert
  • 89.05
  • group
  • 66.4
Validation stages
V1
50.00%
V2
57.89%
V2S
35.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.010s 29.172us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.830s 17.176us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.710s 3.430us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.310s 108.513us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.150s 29.536us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.720s 3.357us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.710s 3.430us 0 1 0.00
clkmgr_csr_aliasing 1.150s 29.536us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.030s 36.592us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.660s 115.853us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.470s 39.920us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.010s 29.172us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.970s 14.354us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.720s 2.011us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.970s 14.354us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.950s 16.017us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.870s 21.003us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.730s 33.302us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.730s 33.302us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.830s 17.176us 1 1 100.00
clkmgr_csr_rw 0.710s 3.430us 0 1 0.00
clkmgr_csr_aliasing 1.150s 29.536us 1 1 100.00
clkmgr_same_csr_outstanding 0.980s 24.640us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.830s 17.176us 1 1 100.00
clkmgr_csr_rw 0.710s 3.430us 0 1 0.00
clkmgr_csr_aliasing 1.150s 29.536us 1 1 100.00
clkmgr_same_csr_outstanding 0.980s 24.640us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_tl_intg_err 0.810s 21.279us 0 1 0.00
clkmgr_sec_cm 0.890s 1.125us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 66.854us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 66.854us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 66.854us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 66.854us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.720s 8.120us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.810s 21.279us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.970s 14.354us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.720s 2.011us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 66.854us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.380s 26.695us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.710s 3.430us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.890s 1.125us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.710s 3.430us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.710s 3.430us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.890s 1.125us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.640s 4.347us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.630s 73.015us 0 1 0.00