Simulation Results: dma

 
18/11/2025 16:10:04 sha: 7662858 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 89.8
  • block
  • 97.38
  • branch
  • 95.83
  • statement
  • 96.89
  • expression
  • 94.6
  • toggle
  • 83.12
  • fsm
  • 91.55
  • assertion
  • 95.97
  • covergroup
  • 66.04
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 471.052us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 299.967us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 716.621us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 23.149us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 21.022us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 12.000s 998.194us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 85.284us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 153.339us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 21.022us 1 1 100.00
dma_csr_aliasing 3.000s 85.284us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 94.000s 10407.409us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 1220.000s 209305.632us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 412.000s 164309.246us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 412.000s 164309.246us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 1220.000s 209305.632us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 176.000s 72708.032us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 412.000s 164309.246us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 8.000s 501.117us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 154.000s 29628.328us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 24.952us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 19.638us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 51.110us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 51.110us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 23.149us 1 1 100.00
dma_csr_rw 1.000s 21.022us 1 1 100.00
dma_csr_aliasing 3.000s 85.284us 1 1 100.00
dma_same_csr_outstanding 2.000s 54.434us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 23.149us 1 1 100.00
dma_csr_rw 1.000s 21.022us 1 1 100.00
dma_csr_aliasing 3.000s 85.284us 1 1 100.00
dma_same_csr_outstanding 2.000s 54.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 15.000s 76.587us 1 1 100.00
dma_generic_stress 176.000s 72708.032us 1 1 100.00
dma_handshake_stress 412.000s 164309.246us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 1225.969us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 4.000s 216.858us 1 1 100.00
dma_sec_cm 1.000s 13.280us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 93.000s 22221.042us 1 1 100.00
dma_longer_transfer 7.000s 542.617us 1 1 100.00
dma_stress_all_with_rand_reset 14.000s 6529.925us 0 1 0.00