Simulation Results: edn

 
18/11/2025 16:10:04 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 83.72
  • line
  • 97.68
  • cond
  • 87.86
  • toggle
  • 82.71
  • fsm
  • 51.16
  • branch
  • 92.38
  • assert
  • 96.0
  • group
  • 78.24
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.190s 16.618us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.850s 49.231us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.820s 12.851us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.520s 182.772us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.910s 18.040us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.380s 40.811us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.820s 12.851us 1 1 100.00
edn_csr_aliasing 0.910s 18.040us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.180s 43.383us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.180s 43.383us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.180s 43.383us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.860s 29.023us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.010s 25.478us 1 1 100.00
errs 1 1 100.00
edn_err 0.770s 33.262us 1 1 100.00
disable 2 2 100.00
edn_disable 0.770s 14.169us 1 1 100.00
edn_disable_auto_req_mode 0.920s 77.284us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.150s 218.405us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.050s 15.695us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.790s 27.697us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.460s 49.422us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.460s 49.422us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.850s 49.231us 1 1 100.00
edn_csr_rw 0.820s 12.851us 1 1 100.00
edn_csr_aliasing 0.910s 18.040us 1 1 100.00
edn_same_csr_outstanding 0.960s 69.660us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.850s 49.231us 1 1 100.00
edn_csr_rw 0.820s 12.851us 1 1 100.00
edn_csr_aliasing 0.910s 18.040us 1 1 100.00
edn_same_csr_outstanding 0.960s 69.660us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.440s 51.363us 1 1 100.00
edn_sec_cm 8.060s 1996.858us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.960s 29.051us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.010s 25.478us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.060s 1996.858us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.060s 1996.858us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 8.060s 1996.858us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 8.060s 1996.858us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.010s 25.478us 1 1 100.00
edn_sec_cm 8.060s 1996.858us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.010s 25.478us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.440s 51.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 48.930s 5545.050us 1 1 100.00