Simulation Results: hmac

 
18/11/2025 16:10:04 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 89.74
  • line
  • 99.53
  • cond
  • 96.46
  • toggle
  • 100.0
  • fsm
  • 94.12
  • branch
  • 98.84
  • assert
  • 95.47
  • group
  • 43.75
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.570s 732.367us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.700s 70.786us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.910s 443.112us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 3.920s 2892.591us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.170s 195.803us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.920s 79.240us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.910s 443.112us 1 1 100.00
hmac_csr_aliasing 2.170s 195.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 14.220s 376.012us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 41.690s 7803.115us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.460s 612.575us 1 1 100.00
hmac_test_sha384_vectors 18.730s 3739.273us 1 1 100.00
hmac_test_sha512_vectors 352.970s 26735.170us 1 1 100.00
hmac_test_hmac256_vectors 6.470s 444.204us 1 1 100.00
hmac_test_hmac384_vectors 9.470s 337.244us 1 1 100.00
hmac_test_hmac512_vectors 9.680s 312.910us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 21.350s 7834.482us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 987.350s 12046.875us 1 1 100.00
error 1 1 100.00
hmac_error 32.580s 10348.539us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 2.480s 864.872us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.570s 732.367us 1 1 100.00
hmac_long_msg 14.220s 376.012us 1 1 100.00
hmac_back_pressure 41.690s 7803.115us 1 1 100.00
hmac_datapath_stress 987.350s 12046.875us 1 1 100.00
hmac_burst_wr 21.350s 7834.482us 1 1 100.00
hmac_stress_all 711.040s 15082.787us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.570s 732.367us 1 1 100.00
hmac_long_msg 14.220s 376.012us 1 1 100.00
hmac_back_pressure 41.690s 7803.115us 1 1 100.00
hmac_datapath_stress 987.350s 12046.875us 1 1 100.00
hmac_wipe_secret 2.480s 864.872us 1 1 100.00
hmac_test_sha256_vectors 7.460s 612.575us 1 1 100.00
hmac_test_sha384_vectors 18.730s 3739.273us 1 1 100.00
hmac_test_sha512_vectors 352.970s 26735.170us 1 1 100.00
hmac_test_hmac256_vectors 6.470s 444.204us 1 1 100.00
hmac_test_hmac384_vectors 9.470s 337.244us 1 1 100.00
hmac_test_hmac512_vectors 9.680s 312.910us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.570s 732.367us 1 1 100.00
hmac_long_msg 14.220s 376.012us 1 1 100.00
hmac_back_pressure 41.690s 7803.115us 1 1 100.00
hmac_datapath_stress 987.350s 12046.875us 1 1 100.00
hmac_burst_wr 21.350s 7834.482us 1 1 100.00
hmac_error 32.580s 10348.539us 1 1 100.00
hmac_wipe_secret 2.480s 864.872us 1 1 100.00
hmac_test_sha256_vectors 7.460s 612.575us 1 1 100.00
hmac_test_sha384_vectors 18.730s 3739.273us 1 1 100.00
hmac_test_sha512_vectors 352.970s 26735.170us 1 1 100.00
hmac_test_hmac256_vectors 6.470s 444.204us 1 1 100.00
hmac_test_hmac384_vectors 9.470s 337.244us 1 1 100.00
hmac_test_hmac512_vectors 9.680s 312.910us 1 1 100.00
hmac_stress_all 711.040s 15082.787us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 711.040s 15082.787us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.600s 29.014us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.590s 18.163us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.070s 482.400us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.070s 482.400us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.700s 70.786us 1 1 100.00
hmac_csr_rw 0.910s 443.112us 1 1 100.00
hmac_csr_aliasing 2.170s 195.803us 1 1 100.00
hmac_same_csr_outstanding 0.880s 82.270us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.700s 70.786us 1 1 100.00
hmac_csr_rw 0.910s 443.112us 1 1 100.00
hmac_csr_aliasing 2.170s 195.803us 1 1 100.00
hmac_same_csr_outstanding 0.880s 82.270us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.970s 357.814us 1 1 100.00
hmac_tl_intg_err 1.410s 95.362us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.410s 95.362us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.570s 732.367us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.980s 173.196us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 458.310s 32135.272us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.080s 331.732us 1 1 100.00