| host_error_intr |
0 |
1 |
0.00 |
|
i2c_host_error_intr |
2.680s |
295.035us |
0 |
1 |
0.00
|
| host_stress_all |
0 |
1 |
0.00 |
|
i2c_host_stress_all |
1.550s |
494.579us |
0 |
1 |
0.00
|
| host_maxperf |
1 |
1 |
100.00 |
|
i2c_host_perf |
1.100s |
546.745us |
1 |
1 |
100.00
|
| host_override |
1 |
1 |
100.00 |
|
i2c_host_override |
0.880s |
15.508us |
1 |
1 |
100.00
|
| host_fifo_watermark |
1 |
1 |
100.00 |
|
i2c_host_fifo_watermark |
163.690s |
3932.623us |
1 |
1 |
100.00
|
| host_fifo_overflow |
1 |
1 |
100.00 |
|
i2c_host_fifo_overflow |
37.490s |
26739.107us |
1 |
1 |
100.00
|
| host_fifo_reset |
3 |
3 |
100.00 |
|
i2c_host_fifo_reset_fmt |
0.740s |
65.473us |
1 |
1 |
100.00
|
|
i2c_host_fifo_fmt_empty |
5.110s |
345.826us |
1 |
1 |
100.00
|
|
i2c_host_fifo_reset_rx |
2.030s |
237.876us |
1 |
1 |
100.00
|
| host_fifo_full |
1 |
1 |
100.00 |
|
i2c_host_fifo_full |
100.360s |
2651.585us |
1 |
1 |
100.00
|
| host_timeout |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
25.140s |
3371.477us |
1 |
1 |
100.00
|
| i2c_host_mode_toggle |
1 |
1 |
100.00 |
|
i2c_host_mode_toggle |
1.770s |
153.918us |
1 |
1 |
100.00
|
| target_glitch |
0 |
1 |
0.00 |
|
i2c_target_glitch |
2.290s |
509.429us |
0 |
1 |
0.00
|
| target_stress_all |
1 |
1 |
100.00 |
|
i2c_target_stress_all |
32.430s |
135046.454us |
1 |
1 |
100.00
|
| target_maxperf |
1 |
1 |
100.00 |
|
i2c_target_perf |
3.390s |
3303.986us |
1 |
1 |
100.00
|
| target_fifo_empty |
2 |
2 |
100.00 |
|
i2c_target_stress_rd |
7.920s |
646.731us |
1 |
1 |
100.00
|
|
i2c_target_intr_smoke |
4.930s |
1272.913us |
1 |
1 |
100.00
|
| target_fifo_reset |
2 |
2 |
100.00 |
|
i2c_target_fifo_reset_acq |
0.990s |
271.343us |
1 |
1 |
100.00
|
|
i2c_target_fifo_reset_tx |
1.090s |
639.860us |
1 |
1 |
100.00
|
| target_fifo_full |
3 |
3 |
100.00 |
|
i2c_target_stress_wr |
147.400s |
48789.027us |
1 |
1 |
100.00
|
|
i2c_target_stress_rd |
7.920s |
646.731us |
1 |
1 |
100.00
|
|
i2c_target_intr_stress_wr |
185.530s |
19842.097us |
1 |
1 |
100.00
|
| target_timeout |
1 |
1 |
100.00 |
|
i2c_target_timeout |
4.550s |
1359.746us |
1 |
1 |
100.00
|
| target_clock_stretch |
1 |
1 |
100.00 |
|
i2c_target_stretch |
1.440s |
519.612us |
1 |
1 |
100.00
|
| bad_address |
1 |
1 |
100.00 |
|
i2c_target_bad_addr |
3.510s |
1765.980us |
1 |
1 |
100.00
|
| target_mode_glitch |
0 |
1 |
0.00 |
|
i2c_target_hrst |
18.250s |
10003.089us |
0 |
1 |
0.00
|
| target_fifo_watermark |
2 |
2 |
100.00 |
|
i2c_target_fifo_watermarks_acq |
2.330s |
583.959us |
1 |
1 |
100.00
|
|
i2c_target_fifo_watermarks_tx |
1.160s |
123.819us |
1 |
1 |
100.00
|
| host_mode_config_perf |
2 |
2 |
100.00 |
|
i2c_host_perf |
1.100s |
546.745us |
1 |
1 |
100.00
|
|
i2c_host_perf_precise |
91.340s |
2428.985us |
1 |
1 |
100.00
|
| host_mode_clock_stretching |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
25.140s |
3371.477us |
1 |
1 |
100.00
|
| target_mode_tx_stretch_ctrl |
1 |
1 |
100.00 |
|
i2c_target_tx_stretch_ctrl |
1.410s |
70.946us |
1 |
1 |
100.00
|
| target_mode_nack_generation |
3 |
3 |
100.00 |
|
i2c_target_nack_acqfull |
2.030s |
456.929us |
1 |
1 |
100.00
|
|
i2c_target_nack_acqfull_addr |
1.830s |
1479.626us |
1 |
1 |
100.00
|
|
i2c_target_nack_txstretch |
1.240s |
314.854us |
1 |
1 |
100.00
|
| host_mode_halt_on_nak |
1 |
1 |
100.00 |
|
i2c_host_may_nack |
5.710s |
2141.478us |
1 |
1 |
100.00
|
| target_mode_smbus_maxlen |
1 |
1 |
100.00 |
|
i2c_target_smbus_maxlen |
1.570s |
3391.462us |
1 |
1 |
100.00
|
| alert_test |
1 |
1 |
100.00 |
|
i2c_alert_test |
0.680s |
17.944us |
1 |
1 |
100.00
|
| intr_test |
1 |
1 |
100.00 |
|
i2c_intr_test |
0.850s |
19.192us |
1 |
1 |
100.00
|
| tl_d_oob_addr_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
1.710s |
141.639us |
1 |
1 |
100.00
|
| tl_d_illegal_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
1.710s |
141.639us |
1 |
1 |
100.00
|
| tl_d_outstanding_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.870s |
59.797us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.820s |
53.584us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.040s |
123.530us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
1.300s |
75.374us |
1 |
1 |
100.00
|
| tl_d_partial_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.870s |
59.797us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.820s |
53.584us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.040s |
123.530us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
1.300s |
75.374us |
1 |
1 |
100.00
|