Simulation Results: lc_ctrl

 
18/11/2025 16:10:04 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 88.44
  • line
  • 97.61
  • cond
  • 79.87
  • toggle
  • 82.42
  • fsm
  • 79.07
  • branch
  • 95.8
  • assert
  • 95.99
  • group
  • 88.31
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
lc_ctrl_smoke 4.540s 699.713us 2 2 100.00
csr_hw_reset 2 2 100.00
lc_ctrl_csr_hw_reset 1.160s 30.292us 2 2 100.00
csr_rw 2 2 100.00
lc_ctrl_csr_rw 1.000s 23.768us 2 2 100.00
csr_bit_bash 2 2 100.00
lc_ctrl_csr_bit_bash 2.310s 160.299us 2 2 100.00
csr_aliasing 2 2 100.00
lc_ctrl_csr_aliasing 1.420s 37.095us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.400s 23.411us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
lc_ctrl_csr_rw 1.000s 23.768us 2 2 100.00
lc_ctrl_csr_aliasing 1.420s 37.095us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 2 50.00
lc_ctrl_state_post_trans 3.940s 123.654us 1 2 50.00
regwen_during_op 2 2 100.00
lc_ctrl_regwen_during_op 12.590s 1220.653us 2 2 100.00
rand_wr_claim_transition_if 2 2 100.00
lc_ctrl_claim_transition_if 0.860s 33.334us 2 2 100.00
lc_prog_failure 2 2 100.00
lc_ctrl_prog_failure 2.040s 174.190us 2 2 100.00
lc_state_failure 0 2 0.00
lc_ctrl_state_failure 6.210s 127.220us 0 2 0.00
lc_errors 2 2 100.00
lc_ctrl_errors 6.460s 1583.484us 2 2 100.00
security_escalation 10 14 71.43
lc_ctrl_state_failure 6.210s 127.220us 0 2 0.00
lc_ctrl_prog_failure 2.040s 174.190us 2 2 100.00
lc_ctrl_errors 6.460s 1583.484us 2 2 100.00
lc_ctrl_security_escalation 6.570s 278.842us 2 2 100.00
lc_ctrl_jtag_state_failure 14.320s 8513.408us 0 2 0.00
lc_ctrl_jtag_prog_failure 5.680s 1028.815us 2 2 100.00
lc_ctrl_jtag_errors 35.430s 9014.912us 2 2 100.00
jtag_access 25 26 96.15
lc_ctrl_jtag_csr_hw_reset 2.250s 510.723us 2 2 100.00
lc_ctrl_jtag_csr_rw 1.400s 140.125us 2 2 100.00
lc_ctrl_jtag_csr_bit_bash 26.050s 6355.709us 2 2 100.00
lc_ctrl_jtag_csr_aliasing 4.070s 403.325us 2 2 100.00
lc_ctrl_jtag_same_csr_outstanding 1.660s 97.733us 2 2 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.020s 134.208us 2 2 100.00
lc_ctrl_jtag_alert_test 2.090s 73.253us 2 2 100.00
lc_ctrl_jtag_smoke 6.250s 711.277us 2 2 100.00
lc_ctrl_jtag_state_post_trans 13.860s 2577.207us 1 2 50.00
lc_ctrl_jtag_prog_failure 5.680s 1028.815us 2 2 100.00
lc_ctrl_jtag_errors 35.430s 9014.912us 2 2 100.00
lc_ctrl_jtag_access 2.150s 802.112us 2 2 100.00
lc_ctrl_jtag_regwen_during_op 17.870s 870.434us 2 2 100.00
jtag_priority 2 2 100.00
lc_ctrl_jtag_priority 2.290s 263.239us 2 2 100.00
lc_ctrl_volatile_unlock 2 2 100.00
lc_ctrl_volatile_unlock_smoke 0.930s 29.444us 2 2 100.00
stress_all 0 2 0.00
lc_ctrl_stress_all 101.750s 23116.883us 0 2 0.00
alert_test 2 2 100.00
lc_ctrl_alert_test 1.150s 48.355us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
lc_ctrl_tl_errors 3.520s 201.043us 2 2 100.00
tl_d_illegal_access 2 2 100.00
lc_ctrl_tl_errors 3.520s 201.043us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
lc_ctrl_csr_hw_reset 1.160s 30.292us 2 2 100.00
lc_ctrl_csr_rw 1.000s 23.768us 2 2 100.00
lc_ctrl_csr_aliasing 1.420s 37.095us 2 2 100.00
lc_ctrl_same_csr_outstanding 1.330s 78.224us 2 2 100.00
tl_d_partial_access 8 8 100.00
lc_ctrl_csr_hw_reset 1.160s 30.292us 2 2 100.00
lc_ctrl_csr_rw 1.000s 23.768us 2 2 100.00
lc_ctrl_csr_aliasing 1.420s 37.095us 2 2 100.00
lc_ctrl_same_csr_outstanding 1.330s 78.224us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 4 4 100.00
lc_ctrl_tl_intg_err 2.040s 113.992us 2 2 100.00
lc_ctrl_sec_cm 5.640s 117.410us 2 2 100.00
sec_cm_bus_integrity 2 2 100.00
lc_ctrl_tl_intg_err 2.040s 113.992us 2 2 100.00
sec_cm_transition_config_regwen 2 2 100.00
lc_ctrl_regwen_during_op 12.590s 1220.653us 2 2 100.00
sec_cm_manuf_state_sparse 2 4 50.00
lc_ctrl_state_failure 6.210s 127.220us 0 2 0.00
lc_ctrl_sec_cm 5.640s 117.410us 2 2 100.00
sec_cm_transition_ctr_sparse 2 4 50.00
lc_ctrl_state_failure 6.210s 127.220us 0 2 0.00
lc_ctrl_sec_cm 5.640s 117.410us 2 2 100.00
sec_cm_manuf_state_bkgn_chk 2 4 50.00
lc_ctrl_state_failure 6.210s 127.220us 0 2 0.00
lc_ctrl_sec_cm 5.640s 117.410us 2 2 100.00
sec_cm_transition_ctr_bkgn_chk 2 4 50.00
lc_ctrl_state_failure 6.210s 127.220us 0 2 0.00
lc_ctrl_sec_cm 5.640s 117.410us 2 2 100.00
sec_cm_state_config_sparse 2 4 50.00
lc_ctrl_state_failure 6.210s 127.220us 0 2 0.00
lc_ctrl_sec_cm 5.640s 117.410us 2 2 100.00
sec_cm_main_fsm_sparse 2 4 50.00
lc_ctrl_state_failure 6.210s 127.220us 0 2 0.00
lc_ctrl_sec_cm 5.640s 117.410us 2 2 100.00
sec_cm_kmac_fsm_sparse 2 4 50.00
lc_ctrl_state_failure 6.210s 127.220us 0 2 0.00
lc_ctrl_sec_cm 5.640s 117.410us 2 2 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
lc_ctrl_state_failure 6.210s 127.220us 0 2 0.00
lc_ctrl_sec_cm 5.640s 117.410us 2 2 100.00
sec_cm_main_fsm_global_esc 2 2 100.00
lc_ctrl_security_escalation 6.570s 278.842us 2 2 100.00
sec_cm_main_ctrl_flow_consistency 2 4 50.00
lc_ctrl_state_post_trans 3.940s 123.654us 1 2 50.00
lc_ctrl_jtag_state_post_trans 13.860s 2577.207us 1 2 50.00
sec_cm_intersig_mubi 2 2 100.00
lc_ctrl_sec_mubi 7.850s 558.276us 2 2 100.00
sec_cm_token_valid_ctrl_mubi 2 2 100.00
lc_ctrl_sec_mubi 7.850s 558.276us 2 2 100.00
sec_cm_token_digest 2 2 100.00
lc_ctrl_sec_token_digest 5.800s 526.720us 2 2 100.00
sec_cm_token_mux_ctrl_redun 2 2 100.00
lc_ctrl_sec_token_mux 7.110s 353.050us 2 2 100.00
sec_cm_token_valid_mux_redun 2 2 100.00
lc_ctrl_sec_token_mux 7.110s 353.050us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 2 0.00
lc_ctrl_stress_all_with_rand_reset 8.590s 547.361us 0 2 0.00