| V1 |
|
100.00% |
| V2 |
|
93.75% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 34.000s | 15895.693us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 18.634us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 1.000s | 23.773us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 2.000s | 133.453us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 1.000s | 54.973us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 2.000s | 33.559us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 1.000s | 23.773us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 54.973us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 1 | 1 | 100.00 | |||
| mbx_stress | 42.000s | 9961.635us | 1 | 1 | 100.00 | |
| mbx_max_activity | 0 | 1 | 0.00 | |||
| mbx_stress_zero_delays | 13.000s | 368.253us | 0 | 1 | 0.00 | |
| mbx_imbx_oob | 1 | 1 | 100.00 | |||
| mbx_imbx_oob | 32.000s | 866.853us | 1 | 1 | 100.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 17.000s | 1087.015us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 1.000s | 13.096us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 2.000s | 17.172us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 3.000s | 573.076us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 3.000s | 573.076us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 18.634us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 23.773us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 54.973us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 177.152us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 18.634us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 23.773us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 54.973us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 177.152us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_sec_cm | 1.000s | 18.568us | 1 | 1 | 100.00 | |
| mbx_tl_intg_err | 2.000s | 559.222us | 1 | 1 | 100.00 | |