Simulation Results: rom_ctrl

 
18/11/2025 16:10:04 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 98.41
  • line
  • 99.46
  • cond
  • 97.03
  • toggle
  • 99.64
  • fsm
  • 100.0
  • branch
  • 98.54
  • assert
  • 96.8
  • group
  • 97.37
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 11.320s 9035.223us 2 2 100.00
csr_hw_reset 2 2 100.00
rom_ctrl_csr_hw_reset 11.030s 294.239us 2 2 100.00
csr_rw 2 2 100.00
rom_ctrl_csr_rw 8.840s 673.158us 2 2 100.00
csr_bit_bash 2 2 100.00
rom_ctrl_csr_bit_bash 7.480s 209.247us 2 2 100.00
csr_aliasing 2 2 100.00
rom_ctrl_csr_aliasing 9.340s 295.914us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.630s 215.471us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
rom_ctrl_csr_rw 8.840s 673.158us 2 2 100.00
rom_ctrl_csr_aliasing 9.340s 295.914us 2 2 100.00
mem_walk 2 2 100.00
rom_ctrl_mem_walk 10.740s 1049.234us 2 2 100.00
mem_partial_access 2 2 100.00
rom_ctrl_mem_partial_access 7.910s 209.232us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 7.050s 222.681us 2 2 100.00
stress_all 2 2 100.00
rom_ctrl_stress_all 19.770s 589.721us 2 2 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 14.500s 1083.363us 2 2 100.00
alert_test 2 2 100.00
rom_ctrl_alert_test 7.430s 292.818us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
rom_ctrl_tl_errors 9.640s 1563.624us 2 2 100.00
tl_d_illegal_access 2 2 100.00
rom_ctrl_tl_errors 9.640s 1563.624us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
rom_ctrl_csr_hw_reset 11.030s 294.239us 2 2 100.00
rom_ctrl_csr_rw 8.840s 673.158us 2 2 100.00
rom_ctrl_csr_aliasing 9.340s 295.914us 2 2 100.00
rom_ctrl_same_csr_outstanding 6.010s 674.238us 2 2 100.00
tl_d_partial_access 8 8 100.00
rom_ctrl_csr_hw_reset 11.030s 294.239us 2 2 100.00
rom_ctrl_csr_rw 8.840s 673.158us 2 2 100.00
rom_ctrl_csr_aliasing 9.340s 295.914us 2 2 100.00
rom_ctrl_same_csr_outstanding 6.010s 674.238us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 103.460s 4949.656us 2 2 100.00
passthru_mem_tl_intg_err 2 2 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.360s 2115.524us 2 2 100.00
tl_intg_err 3 4 75.00
rom_ctrl_sec_cm 232.840s 493.972us 1 2 50.00
rom_ctrl_tl_intg_err 98.170s 601.725us 2 2 100.00
prim_fsm_check 1 2 50.00
rom_ctrl_sec_cm 232.840s 493.972us 1 2 50.00
prim_count_check 1 2 50.00
rom_ctrl_sec_cm 232.840s 493.972us 1 2 50.00
sec_cm_checker_ctr_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 103.460s 4949.656us 2 2 100.00
sec_cm_checker_ctrl_flow_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 103.460s 4949.656us 2 2 100.00
sec_cm_checker_fsm_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 103.460s 4949.656us 2 2 100.00
sec_cm_compare_ctrl_flow_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 103.460s 4949.656us 2 2 100.00
sec_cm_compare_ctr_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 103.460s 4949.656us 2 2 100.00
sec_cm_compare_ctr_redun 1 2 50.00
rom_ctrl_sec_cm 232.840s 493.972us 1 2 50.00
sec_cm_fsm_sparse 1 2 50.00
rom_ctrl_sec_cm 232.840s 493.972us 1 2 50.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 11.320s 9035.223us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 11.320s 9035.223us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 11.320s 9035.223us 2 2 100.00
sec_cm_bus_integrity 2 2 100.00
rom_ctrl_tl_intg_err 98.170s 601.725us 2 2 100.00
sec_cm_bus_local_esc 4 4 100.00
rom_ctrl_corrupt_sig_fatal_chk 103.460s 4949.656us 2 2 100.00
rom_ctrl_kmac_err_chk 14.500s 1083.363us 2 2 100.00
sec_cm_mux_mubi 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 103.460s 4949.656us 2 2 100.00
sec_cm_mux_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 103.460s 4949.656us 2 2 100.00
sec_cm_ctrl_redun 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 103.460s 4949.656us 2 2 100.00
sec_cm_ctrl_mem_integrity 2 2 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.360s 2115.524us 2 2 100.00
sec_cm_tlul_fifo_ctr_redun 1 2 50.00
rom_ctrl_sec_cm 232.840s 493.972us 1 2 50.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 2 100.00
rom_ctrl_stress_all_with_rand_reset 132.930s 19866.409us 2 2 100.00