Simulation Results: rv_dm

 
18/11/2025 16:10:04 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 74.93
  • line
  • 90.06
  • cond
  • 74.09
  • toggle
  • 70.66
  • fsm
  • 56.25
  • branch
  • 74.57
  • assert
  • 96.16
  • group
  • 62.72
Validation stages
V1
93.55%
V2
60.71%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 8.220s 4120.913us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 1.380s 235.931us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 1.120s 214.443us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 9.950s 14353.927us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 0.760s 234.872us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 11.010s 8056.408us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 4.260s 1964.421us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 9.050s 18467.834us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 241.360s 119169.202us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 1.110s 268.589us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 1.000s 182.573us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 0.940s 204.814us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 0.830s 194.247us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 1.110s 307.598us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 1.690s 695.998us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 0.870s 191.962us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 0.880s 201.621us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 1.110s 268.589us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 0.870s 686.935us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 2.100s 832.050us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 0.940s 204.814us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.790s 33.367us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.820s 253.124us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.870s 95.173us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 61.440s 28119.564us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 17.160s 1300.490us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
rv_dm_csr_mem_rw_with_rand_reset 0.790s 32.487us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 17.160s 1300.490us 1 1 100.00
rv_dm_csr_rw 1.870s 95.173us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.750s 44.222us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.660s 149.014us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 8.220s 4120.913us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 1.010s 194.081us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 0.920s 295.091us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 0.850s 146.674us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 1.800s 2767.967us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 482.570s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 65.370s 300000.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 213.550s 300000.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 254.040s 300000.000us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 0.770s 307.870us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 1.050s 639.170us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 0.920s 205.865us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.810s 36.094us 0 1 0.00
tap_ctrl_transitions 0 2 0.00
rv_dm_tap_fsm_rand_reset 0.900s 119.573us 0 1 0.00
rv_dm_tap_fsm 22.740s 11887.261us 0 1 0.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.800s 369.697us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 0.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.850s 157.599us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
rv_dm_tl_errors 1.600s 220.121us 0 1 0.00
tl_d_illegal_access 0 1 0.00
rv_dm_tl_errors 1.600s 220.121us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 17.160s 1300.490us 1 1 100.00
rv_dm_csr_hw_reset 1.820s 253.124us 1 1 100.00
rv_dm_csr_rw 1.870s 95.173us 1 1 100.00
rv_dm_same_csr_outstanding 5.430s 532.363us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 17.160s 1300.490us 1 1 100.00
rv_dm_csr_hw_reset 1.820s 253.124us 1 1 100.00
rv_dm_csr_rw 1.870s 95.173us 1 1 100.00
rv_dm_same_csr_outstanding 5.430s 532.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 15.620s 5506.436us 1 1 100.00
rv_dm_sec_cm 0.910s 1070.588us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 15.620s 5506.436us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 1.050s 639.170us 1 1 100.00
rv_dm_debug_disabled 1.070s 139.272us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 1.050s 639.170us 1 1 100.00
rv_dm_debug_disabled 1.070s 139.272us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 8.220s 4120.913us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 1.030s 96.135us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.740s 125.994us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.740s 125.994us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 1.030s 96.135us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 1.150s 130.649us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 568.780s 300000.000us 0 1 0.00