Simulation Results: spi_device

 
18/11/2025 16:10:04 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 87.92
  • line
  • 99.05
  • cond
  • 95.99
  • toggle
  • 83.54
  • fsm
  • 89.36
  • branch
  • 98.28
  • assert
  • 86.87
  • group
  • 62.35
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 17.660s 2504.674us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.080s 43.134us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.110s 125.832us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 7.360s 189.361us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 4.720s 108.909us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.940s 340.399us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.110s 125.832us 1 1 100.00
spi_device_csr_aliasing 4.720s 108.909us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.740s 13.775us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.310s 83.857us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.840s 51.633us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.930s 7.975us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.850s 3.347us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.850s 12.889us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.850s 12.889us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 10.630s 6428.470us 1 1 100.00
spi_device_tpm_sts_read 1.050s 71.756us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 33.670s 8691.050us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.540s 381.402us 1 1 100.00
spi_device_flash_all 54.240s 49574.327us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.200s 288.786us 1 1 100.00
spi_device_flash_all 54.240s 49574.327us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.200s 288.786us 1 1 100.00
spi_device_flash_all 54.240s 49574.327us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 54.240s 49574.327us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.280s 1802.841us 1 1 100.00
spi_device_flash_all 54.240s 49574.327us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.280s 1802.841us 1 1 100.00
spi_device_flash_all 54.240s 49574.327us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.280s 1802.841us 1 1 100.00
spi_device_flash_all 54.240s 49574.327us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.280s 1802.841us 1 1 100.00
spi_device_flash_all 54.240s 49574.327us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.280s 1802.841us 1 1 100.00
spi_device_flash_all 54.240s 49574.327us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 9.320s 7712.426us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 6.220s 1963.877us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 6.220s 1963.877us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 6.220s 1963.877us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 22.530s 6786.323us 1 1 100.00
spi_device_read_buffer_direct 5.940s 5573.381us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 6.220s 1963.877us 1 1 100.00
spi_device_flash_all 54.240s 49574.327us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 54.240s 49574.327us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 54.240s 49574.327us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.310s 217.421us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.310s 217.421us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 17.660s 2504.674us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 9.140s 7095.083us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 176.200s 71708.946us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.780s 18.505us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.720s 25.454us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.430s 372.037us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.430s 372.037us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.080s 43.134us 1 1 100.00
spi_device_csr_rw 1.110s 125.832us 1 1 100.00
spi_device_csr_aliasing 4.720s 108.909us 1 1 100.00
spi_device_same_csr_outstanding 2.150s 317.780us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.080s 43.134us 1 1 100.00
spi_device_csr_rw 1.110s 125.832us 1 1 100.00
spi_device_csr_aliasing 4.720s 108.909us 1 1 100.00
spi_device_same_csr_outstanding 2.150s 317.780us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.500s 71.281us 1 1 100.00
spi_device_tl_intg_err 8.930s 786.506us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 8.930s 786.506us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 88.770s 56335.688us 1 1 100.00