Simulation Results: spi_host

 
18/11/2025 16:10:04 sha: 7662858 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 95.8
  • block
  • 96.82
  • branch
  • 93.35
  • statement
  • 98.69
  • expression
  • 92.2
  • toggle
  • 88.02
  • fsm
  • 100.0
  • assertion
  • 93.54
  • covergroup
  • 88.75
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 27.000s 2741.057us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 15.384us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 20.870us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 56.631us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 54.723us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 74.410us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 20.870us 1 1 100.00
spi_host_csr_aliasing 2.000s 54.723us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 15.067us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 25.227us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 50.980us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 142.045us 1 1 100.00
spi_host_error_cmd 2.000s 18.888us 1 1 100.00
spi_host_event 17.000s 4678.798us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 129.421us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 129.421us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 129.421us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 5.000s 280.190us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 37.657us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 129.421us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 129.421us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 27.000s 2741.057us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 27.000s 2741.057us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 20.000s 1323.549us 1 1 100.00
spien 1 1 100.00
spi_host_spien 6.000s 378.321us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 7.000s 1015.613us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 422.137us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 142.045us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 90.795us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 29.660us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 218.249us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 218.249us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 15.384us 1 1 100.00
spi_host_csr_rw 2.000s 20.870us 1 1 100.00
spi_host_csr_aliasing 2.000s 54.723us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 20.119us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 15.384us 1 1 100.00
spi_host_csr_rw 2.000s 20.870us 1 1 100.00
spi_host_csr_aliasing 2.000s 54.723us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 20.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 2.000s 74.637us 1 1 100.00
spi_host_tl_intg_err 2.000s 173.498us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 173.498us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 158.000s 13669.078us 1 1 100.00