Simulation Results: sram_ctrl

 
18/11/2025 16:10:04 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 95.88
  • line
  • 98.98
  • cond
  • 91.92
  • toggle
  • 90.5
  • fsm
  • 100.0
  • branch
  • 96.97
  • assert
  • 95.79
  • group
  • 97.03
Validation stages
V1
100.00%
V2
100.00%
V2S
72.92%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
sram_ctrl_smoke 15.730s 2526.440us 2 2 100.00
csr_hw_reset 2 2 100.00
sram_ctrl_csr_hw_reset 0.910s 49.543us 2 2 100.00
csr_rw 2 2 100.00
sram_ctrl_csr_rw 0.910s 28.608us 2 2 100.00
csr_bit_bash 2 2 100.00
sram_ctrl_csr_bit_bash 1.790s 101.261us 2 2 100.00
csr_aliasing 2 2 100.00
sram_ctrl_csr_aliasing 1.030s 50.558us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.530s 376.916us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
sram_ctrl_csr_rw 0.910s 28.608us 2 2 100.00
sram_ctrl_csr_aliasing 1.030s 50.558us 2 2 100.00
mem_walk 2 2 100.00
sram_ctrl_mem_walk 268.620s 41410.580us 2 2 100.00
mem_partial_access 2 2 100.00
sram_ctrl_mem_partial_access 47.970s 4168.641us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 2 2 100.00
sram_ctrl_multiple_keys 508.300s 5313.555us 2 2 100.00
stress_pipeline 2 2 100.00
sram_ctrl_stress_pipeline 209.520s 20656.181us 2 2 100.00
bijection 2 2 100.00
sram_ctrl_bijection 1669.330s 143721.038us 2 2 100.00
access_during_key_req 2 2 100.00
sram_ctrl_access_during_key_req 563.560s 5475.187us 2 2 100.00
lc_escalation 2 2 100.00
sram_ctrl_lc_escalation 64.270s 49996.471us 2 2 100.00
executable 2 2 100.00
sram_ctrl_executable 223.740s 7997.121us 2 2 100.00
partial_access 4 4 100.00
sram_ctrl_partial_access 14.340s 3969.813us 2 2 100.00
sram_ctrl_partial_access_b2b 265.870s 12575.706us 2 2 100.00
max_throughput 6 6 100.00
sram_ctrl_max_throughput 13.980s 86.276us 2 2 100.00
sram_ctrl_throughput_w_partial_write 20.990s 123.670us 2 2 100.00
sram_ctrl_throughput_w_readback 61.910s 573.314us 2 2 100.00
regwen 2 2 100.00
sram_ctrl_regwen 475.170s 45616.485us 2 2 100.00
ram_cfg 2 2 100.00
sram_ctrl_ram_cfg 2.170s 352.529us 2 2 100.00
stress_all 2 2 100.00
sram_ctrl_stress_all 2527.510s 108555.784us 2 2 100.00
alert_test 2 2 100.00
sram_ctrl_alert_test 0.960s 12.650us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
sram_ctrl_tl_errors 3.680s 121.908us 2 2 100.00
tl_d_illegal_access 2 2 100.00
sram_ctrl_tl_errors 3.680s 121.908us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
sram_ctrl_csr_hw_reset 0.910s 49.543us 2 2 100.00
sram_ctrl_csr_rw 0.910s 28.608us 2 2 100.00
sram_ctrl_csr_aliasing 1.030s 50.558us 2 2 100.00
sram_ctrl_same_csr_outstanding 1.060s 60.446us 2 2 100.00
tl_d_partial_access 8 8 100.00
sram_ctrl_csr_hw_reset 0.910s 49.543us 2 2 100.00
sram_ctrl_csr_rw 0.910s 28.608us 2 2 100.00
sram_ctrl_csr_aliasing 1.030s 50.558us 2 2 100.00
sram_ctrl_same_csr_outstanding 1.060s 60.446us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 2 2 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.900s 3869.485us 2 2 100.00
tl_intg_err 2 4 50.00
sram_ctrl_sec_cm 0.840s 1.370us 0 2 0.00
sram_ctrl_tl_intg_err 2.310s 1294.149us 2 2 100.00
prim_count_check 0 2 0.00
sram_ctrl_sec_cm 0.840s 1.370us 0 2 0.00
sec_cm_bus_integrity 2 2 100.00
sram_ctrl_tl_intg_err 2.310s 1294.149us 2 2 100.00
sec_cm_ctrl_config_regwen 2 2 100.00
sram_ctrl_regwen 475.170s 45616.485us 2 2 100.00
sec_cm_readback_config_regwen 2 2 100.00
sram_ctrl_regwen 475.170s 45616.485us 2 2 100.00
sec_cm_exec_config_regwen 2 2 100.00
sram_ctrl_csr_rw 0.910s 28.608us 2 2 100.00
sec_cm_exec_config_mubi 2 2 100.00
sram_ctrl_executable 223.740s 7997.121us 2 2 100.00
sec_cm_exec_intersig_mubi 2 2 100.00
sram_ctrl_executable 223.740s 7997.121us 2 2 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
sram_ctrl_executable 223.740s 7997.121us 2 2 100.00
sec_cm_lc_escalate_en_intersig_mubi 2 2 100.00
sram_ctrl_lc_escalation 64.270s 49996.471us 2 2 100.00
sec_cm_prim_ram_ctrl_mubi 1 2 50.00
sram_ctrl_mubi_enc_err 3.910s 684.612us 1 2 50.00
sec_cm_mem_integrity 2 2 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.900s 3869.485us 2 2 100.00
sec_cm_mem_readback 2 2 100.00
sram_ctrl_readback_err 3.830s 3012.250us 2 2 100.00
sec_cm_mem_scramble 2 2 100.00
sram_ctrl_smoke 15.730s 2526.440us 2 2 100.00
sec_cm_addr_scramble 2 2 100.00
sram_ctrl_smoke 15.730s 2526.440us 2 2 100.00
sec_cm_instr_bus_lc_gated 2 2 100.00
sram_ctrl_executable 223.740s 7997.121us 2 2 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 2 0.00
sram_ctrl_sec_cm 0.840s 1.370us 0 2 0.00
sec_cm_key_global_esc 2 2 100.00
sram_ctrl_lc_escalation 64.270s 49996.471us 2 2 100.00
sec_cm_key_local_esc 0 2 0.00
sram_ctrl_sec_cm 0.840s 1.370us 0 2 0.00
sec_cm_init_ctr_redun 0 2 0.00
sram_ctrl_sec_cm 0.840s 1.370us 0 2 0.00
sec_cm_scramble_key_sideload 2 2 100.00
sram_ctrl_smoke 15.730s 2526.440us 2 2 100.00
sec_cm_tlul_fifo_ctr_redun 0 2 0.00
sram_ctrl_sec_cm 0.840s 1.370us 0 2 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 2 100.00
sram_ctrl_stress_all_with_rand_reset 30.180s 3273.047us 2 2 100.00