Simulation Results: uart

 
18/11/2025 16:10:04 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 89.75
  • line
  • 99.48
  • cond
  • 97.55
  • toggle
  • 91.55
  • fsm
  • None
  • branch
  • 98.14
  • assert
  • 97.12
  • group
  • 54.67
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.670s 668.806us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.690s 34.659us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.650s 51.959us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.980s 671.887us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.800s 107.694us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.890s 22.922us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.650s 51.959us 1 1 100.00
uart_csr_aliasing 0.800s 107.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 6.940s 8984.942us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.670s 668.806us 1 1 100.00
uart_tx_rx 6.940s 8984.942us 1 1 100.00
parity_error 2 2 100.00
uart_intr 9.810s 23958.316us 1 1 100.00
uart_rx_parity_err 19.970s 19773.348us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 6.940s 8984.942us 1 1 100.00
uart_intr 9.810s 23958.316us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 7.850s 28105.931us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 27.100s 57615.581us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 32.130s 32007.470us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 9.810s 23958.316us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 9.810s 23958.316us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 9.810s 23958.316us 1 1 100.00
perf 1 1 100.00
uart_perf 355.040s 10235.806us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 14.530s 9920.221us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 14.530s 9920.221us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 8.450s 11126.792us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 5.520s 3892.240us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.770s 2504.928us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 12.020s 4127.940us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 584.430s 107426.069us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 219.620s 147862.619us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.660s 63.676us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.710s 59.280us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.020s 37.686us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.020s 37.686us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.690s 34.659us 1 1 100.00
uart_csr_rw 0.650s 51.959us 1 1 100.00
uart_csr_aliasing 0.800s 107.694us 1 1 100.00
uart_same_csr_outstanding 0.700s 22.558us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.690s 34.659us 1 1 100.00
uart_csr_rw 0.650s 51.959us 1 1 100.00
uart_csr_aliasing 0.800s 107.694us 1 1 100.00
uart_same_csr_outstanding 0.700s 22.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_tl_intg_err 1.200s 302.515us 1 1 100.00
uart_sec_cm 0.920s 40.705us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.200s 302.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 33.340s 9538.730us 1 1 100.00