| chip_sw_spi_device_flash_mode |
0 |
1 |
0.00 |
|
chip_sw_uart_tx_rx_bootstrap |
88.776s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_spi_device_pass_through |
1 |
1 |
100.00 |
|
chip_sw_spi_device_pass_through |
2228.280s |
3590.889us |
1 |
1 |
100.00
|
| chip_sw_spi_device_pass_through_collision |
0 |
1 |
0.00 |
|
chip_sw_spi_device_pass_through_collision |
190.740s |
163.980us |
0 |
1 |
0.00
|
| chip_sw_spi_device_tpm |
0 |
1 |
0.00 |
|
chip_sw_spi_device_tpm |
30.666s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_spi_host_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_spi_host_tx_rx |
34.519s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_i2c_host_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_i2c_host_tx_rx |
37.170s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_i2c_device_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_i2c_device_tx_rx |
30.228s |
0.000us |
0 |
1 |
0.00
|
| chip_pin_mux |
0 |
1 |
0.00 |
|
chip_padctrl_attributes |
2.640s |
0.000us |
0 |
1 |
0.00
|
| chip_padctrl_attributes |
0 |
1 |
0.00 |
|
chip_padctrl_attributes |
2.640s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sleep_pin_wake |
0 |
1 |
0.00 |
|
chip_sw_sleep_pin_wake |
102.061s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sleep_pin_retention |
0 |
1 |
0.00 |
|
chip_sw_sleep_pin_retention |
91.844s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_data_integrity |
0 |
1 |
0.00 |
|
chip_sw_data_integrity_escalation |
116.097s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_instruction_integrity |
0 |
1 |
0.00 |
|
chip_sw_data_integrity_escalation |
116.097s |
0.000us |
0 |
1 |
0.00
|
| chip_jtag_csr_rw |
0 |
1 |
0.00 |
|
chip_jtag_csr_rw |
113.530s |
117.021us |
0 |
1 |
0.00
|
| chip_jtag_mem_access |
0 |
1 |
0.00 |
|
chip_jtag_mem_access |
100.670s |
117.021us |
0 |
1 |
0.00
|
| chip_rv_dm_ndm_reset_req |
1 |
1 |
100.00 |
|
chip_rv_dm_ndm_reset_req |
247.180s |
273.270us |
1 |
1 |
100.00
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted |
0 |
1 |
0.00 |
|
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted |
9.303s |
0.000us |
0 |
1 |
0.00
|
| chip_rv_dm_access_after_wakeup |
0 |
1 |
0.00 |
|
chip_sw_rv_dm_access_after_wakeup |
9.899s |
0.000us |
0 |
1 |
0.00
|
| chip_rv_dm_lc_disabled |
0 |
1 |
0.00 |
|
chip_rv_dm_lc_disabled |
180.040s |
243.947us |
0 |
1 |
0.00
|
| chip_sw_timer |
1 |
1 |
100.00 |
|
chip_sw_rv_timer_irq |
231.650s |
248.755us |
1 |
1 |
100.00
|
| chip_sw_aon_timer_wakeup_irq |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_irq |
514.020s |
572.525us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_wdog_bark_irq |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_irq |
514.020s |
572.525us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_wdog_lc_escalate |
1 |
1 |
100.00 |
|
chip_sw_aon_timer_wdog_lc_escalate |
321.970s |
348.530us |
1 |
1 |
100.00
|
| chip_sw_aon_timer_wdog_bite_reset |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
204.470s |
164.336us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_sleep_wdog_bite_reset |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
204.470s |
164.336us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_sleep_wdog_sleep_pause |
1 |
1 |
100.00 |
|
chip_sw_aon_timer_sleep_wdog_sleep_pause |
324.560s |
2271.410us |
1 |
1 |
100.00
|
| chip_sw_plic_sw_irq |
1 |
1 |
100.00 |
|
chip_sw_plic_sw_irq |
157.110s |
145.521us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_idle_trans |
4 |
4 |
100.00 |
|
chip_sw_otbn_randomness |
264.610s |
225.663us |
1 |
1 |
100.00
|
|
chip_sw_aes_idle |
165.650s |
147.255us |
1 |
1 |
100.00
|
|
chip_sw_hmac_enc_idle |
182.940s |
161.540us |
1 |
1 |
100.00
|
|
chip_sw_kmac_idle |
141.360s |
145.063us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_off_trans |
0 |
4 |
0.00 |
|
chip_sw_clkmgr_off_aes_trans |
169.280s |
165.712us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_hmac_trans |
160.550s |
165.680us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_kmac_trans |
171.420s |
165.712us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_otbn_trans |
165.960s |
165.696us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_jitter |
1 |
7 |
14.29 |
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
38.730s |
10.360us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en |
36.870s |
10.360us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en |
45.130s |
10.260us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
42.180s |
10.280us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
45.580s |
10.340us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
13.123s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_jitter |
147.880s |
141.892us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_extended_range |
1 |
8 |
12.50 |
|
chip_sw_clkmgr_jitter_reduced_freq |
324.330s |
1779.654us |
1 |
1 |
100.00
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq |
38.950s |
10.260us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en_reduced_freq |
37.450s |
10.320us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en_reduced_freq |
38.980s |
10.360us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq |
38.030s |
10.280us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq |
41.600s |
10.100us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq |
46.580s |
10.100us |
0 |
1 |
0.00
|
|
chip_sw_csrng_edn_concurrency_reduced_freq |
37.320s |
10.140us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_deep_sleep_frequency |
0 |
1 |
0.00 |
|
chip_sw_ast_clk_outputs |
9.626s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_sleep_frequency |
0 |
1 |
0.00 |
|
chip_sw_clkmgr_sleep_frequency |
10.834s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_reset_frequency |
0 |
1 |
0.00 |
|
chip_sw_clkmgr_reset_frequency |
10.382s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
901.390s |
905.702us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_external_full_reset |
1 |
1 |
100.00 |
|
chip_sw_pwrmgr_full_aon_reset |
352.220s |
485.157us |
1 |
1 |
100.00
|
| chip_sw_pwrmgr_sleep_all_reset_reqs |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
204.470s |
164.336us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_wdog_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_wdog_reset |
11.988s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_aon_power_glitch_reset |
1 |
1 |
100.00 |
|
chip_sw_pwrmgr_full_aon_reset |
352.220s |
485.157us |
1 |
1 |
100.00
|
| chip_sw_pwrmgr_main_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_main_power_glitch_reset |
10.320s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_random_sleep_power_glitch_reset |
9.514s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
9.639s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_sleep_power_glitch_reset |
9.222s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_sleep_disabled |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_sleep_disabled |
11.666s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
901.390s |
905.702us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sys_reset_info |
1 |
1 |
100.00 |
|
chip_rv_dm_ndm_reset_req |
247.180s |
273.270us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_cpu_info |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
327.290s |
375.216us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sw_req_reset |
1 |
1 |
100.00 |
|
chip_sw_rstmgr_sw_req |
261.130s |
267.312us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_alert_info |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_alert_info |
318.560s |
290.090us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sw_rst |
1 |
1 |
100.00 |
|
chip_sw_rstmgr_sw_rst |
152.600s |
144.111us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
901.390s |
905.702us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_alerts |
0 |
1 |
0.00 |
|
chip_sw_alert_test |
9.525s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_escalations |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_escalation |
12.592s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_all_escalation_resets |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
901.390s |
905.702us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_entropy |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_entropy |
12.053s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_crashdump |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_alert_info |
318.560s |
290.090us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_ping_timeout |
1 |
1 |
100.00 |
|
chip_sw_alert_handler_ping_timeout |
186.250s |
201.547us |
1 |
1 |
100.00
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_sleep_mode_alerts |
10.088s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_sleep_mode_pings |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_sleep_mode_pings |
10.587s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_clock_off |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_clkoff |
9.699s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_reset_toggle |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_reset_toggle |
10.080s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_reverse_ping_in_deep_sleep |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_reverse_ping_in_deep_sleep |
10.361s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_alert_handler_escalation |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_escalation |
12.592s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_jtag_access |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
16.558s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_otp_hw_cfg |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_otp_hw_cfg |
14.365s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_init |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
16.558s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_transitions |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
16.558s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_kmac_req |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
16.558s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_key_div |
0 |
1 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation_prod |
264.430s |
268.115us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_broadcast |
2 |
10 |
20.00 |
|
chip_prim_tl_access |
169.870s |
259.586us |
1 |
1 |
100.00
|
|
chip_rv_dm_lc_disabled |
180.040s |
243.947us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_test_unlocked0 |
15.550s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_dev |
16.628s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_prod |
20.923s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_rma |
11.358s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_ctrl_transition |
16.558s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation |
284.150s |
268.108us |
0 |
1 |
0.00
|
|
chip_sw_rom_ctrl_integrity_check |
715.170s |
1266.502us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_execution_main |
10.072s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_aes_enc |
1 |
2 |
50.00 |
|
chip_sw_aes_enc |
190.580s |
157.100us |
1 |
1 |
100.00
|
|
chip_sw_aes_enc_jitter_en |
36.870s |
10.360us |
0 |
1 |
0.00
|
| chip_sw_aes_entropy |
1 |
1 |
100.00 |
|
chip_sw_aes_entropy |
165.820s |
145.885us |
1 |
1 |
100.00
|
| chip_sw_aes_idle |
1 |
1 |
100.00 |
|
chip_sw_aes_idle |
165.650s |
147.255us |
1 |
1 |
100.00
|
| chip_sw_hmac_enc |
1 |
2 |
50.00 |
|
chip_sw_hmac_enc |
185.340s |
156.380us |
1 |
1 |
100.00
|
|
chip_sw_hmac_enc_jitter_en |
45.130s |
10.260us |
0 |
1 |
0.00
|
| chip_sw_hmac_idle |
1 |
1 |
100.00 |
|
chip_sw_hmac_enc_idle |
182.940s |
161.540us |
1 |
1 |
100.00
|
| chip_sw_kmac_enc |
2 |
3 |
66.67 |
|
chip_sw_kmac_mode_cshake |
163.820s |
148.941us |
1 |
1 |
100.00
|
|
chip_sw_kmac_mode_kmac |
196.740s |
172.126us |
1 |
1 |
100.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
45.580s |
10.340us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_keymgr |
0 |
1 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation |
284.150s |
268.108us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_lc |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
16.558s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_rom |
0 |
1 |
0.00 |
|
chip_sw_kmac_app_rom |
30.250s |
10.400us |
0 |
1 |
0.00
|
| chip_sw_kmac_entropy |
1 |
1 |
100.00 |
|
chip_sw_kmac_entropy |
245.810s |
192.574us |
1 |
1 |
100.00
|
| chip_sw_kmac_idle |
1 |
1 |
100.00 |
|
chip_sw_kmac_idle |
141.360s |
145.063us |
1 |
1 |
100.00
|
| chip_sw_entropy_src_csrng |
1 |
1 |
100.00 |
|
chip_sw_entropy_src_csrng |
414.740s |
290.286us |
1 |
1 |
100.00
|
| chip_sw_csrng_edn_cmd |
1 |
1 |
100.00 |
|
chip_sw_entropy_src_csrng |
414.740s |
290.286us |
1 |
1 |
100.00
|
| chip_sw_csrng_fuse_en_sw_app_read |
0 |
1 |
0.00 |
|
chip_sw_csrng_fuse_en_sw_app_read_test |
12.977s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_csrng_known_answer_tests |
1 |
1 |
100.00 |
|
chip_sw_csrng_kat_test |
184.770s |
156.759us |
1 |
1 |
100.00
|
| chip_sw_edn_entropy_reqs |
1 |
1 |
100.00 |
|
chip_sw_csrng_edn_concurrency |
999.460s |
839.460us |
1 |
1 |
100.00
|
| chip_sw_keymgr_dpe_key_derivation |
0 |
2 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation |
284.150s |
268.108us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
42.180s |
10.280us |
0 |
1 |
0.00
|
| chip_sw_otbn_op |
1 |
2 |
50.00 |
|
chip_sw_otbn_ecdsa_op_irq |
2271.850s |
1472.560us |
1 |
1 |
100.00
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
38.730s |
10.360us |
0 |
1 |
0.00
|
| chip_sw_otbn_rnd_entropy |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
264.610s |
225.663us |
1 |
1 |
100.00
|
| chip_sw_otbn_urnd_entropy |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
264.610s |
225.663us |
1 |
1 |
100.00
|
| chip_sw_otbn_idle |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
264.610s |
225.663us |
1 |
1 |
100.00
|
| chip_sw_otbn_mem_scramble |
1 |
1 |
100.00 |
|
chip_sw_otbn_mem_scramble |
377.360s |
264.738us |
1 |
1 |
100.00
|
| chip_sw_rom_access |
1 |
1 |
100.00 |
|
chip_sw_rom_ctrl_integrity_check |
715.170s |
1266.502us |
1 |
1 |
100.00
|
| chip_sw_rom_ctrl_integrity_check |
1 |
1 |
100.00 |
|
chip_sw_rom_ctrl_integrity_check |
715.170s |
1266.502us |
1 |
1 |
100.00
|
| chip_sw_sram_scrambled_access |
1 |
2 |
50.00 |
|
chip_sw_sram_ctrl_scrambled_access |
310.190s |
314.193us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
13.123s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sram_execution |
0 |
1 |
0.00 |
|
chip_sw_sram_ctrl_execution_main |
10.072s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sram_lc_escalation |
0 |
2 |
0.00 |
|
chip_sw_all_escalation_resets |
901.390s |
905.702us |
0 |
1 |
0.00
|
|
chip_sw_data_integrity_escalation |
116.097s |
0.000us |
0 |
1 |
0.00
|
| chip_otp_ctrl_init |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
16.558s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_keys |
3 |
4 |
75.00 |
|
chip_sw_otbn_mem_scramble |
377.360s |
264.738us |
1 |
1 |
100.00
|
|
chip_sw_keymgr_dpe_key_derivation |
284.150s |
268.108us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access |
310.190s |
314.193us |
1 |
1 |
100.00
|
|
chip_sw_rv_core_ibex_icache_invalidate |
167.400s |
160.099us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_entropy |
3 |
4 |
75.00 |
|
chip_sw_otbn_mem_scramble |
377.360s |
264.738us |
1 |
1 |
100.00
|
|
chip_sw_keymgr_dpe_key_derivation |
284.150s |
268.108us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access |
310.190s |
314.193us |
1 |
1 |
100.00
|
|
chip_sw_rv_core_ibex_icache_invalidate |
167.400s |
160.099us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_program |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
16.558s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_program_error |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_program_error |
9.694s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_hw_cfg |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_otp_hw_cfg |
14.365s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_lc_signals |
1 |
6 |
16.67 |
|
chip_prim_tl_access |
169.870s |
259.586us |
1 |
1 |
100.00
|
|
chip_sw_otp_ctrl_lc_signals_test_unlocked0 |
15.550s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_dev |
16.628s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_prod |
20.923s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_rma |
11.358s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_ctrl_transition |
16.558s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_prim_tl_access |
1 |
1 |
100.00 |
|
chip_prim_tl_access |
169.870s |
259.586us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_nvm_cnt |
0 |
1 |
0.00 |
|
chip_sw_otp_ctrl_nvm_cnt |
11.285s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_sw_parts |
0 |
1 |
0.00 |
|
chip_sw_otp_ctrl_sw_parts |
11.184s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_ast_clk_outputs |
0 |
1 |
0.00 |
|
chip_sw_ast_clk_outputs |
9.626s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_ast_sys_clk_jitter |
1 |
7 |
14.29 |
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
38.730s |
10.360us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en |
36.870s |
10.360us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en |
45.130s |
10.260us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
42.180s |
10.280us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
45.580s |
10.340us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
13.123s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_jitter |
147.880s |
141.892us |
1 |
1 |
100.00
|
| chip_sw_soc_proxy_external_reset_requests |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_smoketest |
163.730s |
137.312us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_external_irqs |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_smoketest |
163.730s |
137.312us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_external_wakeup_requests |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_external_wakeup |
163.960s |
138.803us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_gpios |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_gpios |
151.790s |
136.465us |
0 |
1 |
0.00
|
| chip_sw_nmi_irq |
0 |
1 |
0.00 |
|
chip_sw_rv_core_ibex_nmi_irq |
354.540s |
251.518us |
0 |
1 |
0.00
|
| chip_sw_rv_core_ibex_rnd |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_rnd |
241.210s |
195.537us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_address_translation |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_address_translation |
192.600s |
164.751us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_icache_scrambled_access |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_icache_invalidate |
167.400s |
160.099us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_fault_dump |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
327.290s |
375.216us |
0 |
1 |
0.00
|
| chip_sw_rv_core_ibex_double_fault |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
327.290s |
375.216us |
0 |
1 |
0.00
|
| chip_sw_smoketest |
14 |
14 |
100.00 |
|
chip_sw_aes_smoketest |
134.560s |
157.124us |
1 |
1 |
100.00
|
|
chip_sw_aon_timer_smoketest |
151.250s |
163.240us |
1 |
1 |
100.00
|
|
chip_sw_clkmgr_smoketest |
133.660s |
142.943us |
1 |
1 |
100.00
|
|
chip_sw_csrng_smoketest |
119.850s |
144.772us |
1 |
1 |
100.00
|
|
chip_sw_gpio_smoketest |
151.650s |
165.776us |
1 |
1 |
100.00
|
|
chip_sw_hmac_smoketest |
160.100s |
182.002us |
1 |
1 |
100.00
|
|
chip_sw_kmac_smoketest |
150.530s |
171.081us |
1 |
1 |
100.00
|
|
chip_sw_otbn_smoketest |
202.600s |
219.226us |
1 |
1 |
100.00
|
|
chip_sw_otp_ctrl_smoketest |
131.940s |
148.072us |
1 |
1 |
100.00
|
|
chip_sw_rv_plic_smoketest |
137.420s |
145.085us |
1 |
1 |
100.00
|
|
chip_sw_rv_timer_smoketest |
195.510s |
248.771us |
1 |
1 |
100.00
|
|
chip_sw_rstmgr_smoketest |
124.590s |
141.610us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_smoketest |
126.090s |
145.496us |
1 |
1 |
100.00
|
|
chip_sw_uart_smoketest |
133.850s |
157.685us |
1 |
1 |
100.00
|
| chip_sw_rom_functests |
0 |
1 |
0.00 |
|
rom_keymgr_functest |
9.781s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_signed |
0 |
1 |
0.00 |
|
chip_sw_uart_smoketest_signed |
10.045s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_boot |
0 |
1 |
0.00 |
|
chip_sw_uart_tx_rx_bootstrap |
88.776s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_secure_boot |
0 |
1 |
0.00 |
|
base_rom_e2e_smoke |
10.867s |
0.000us |
0 |
1 |
0.00
|
| chip_lc_scrap |
4 |
4 |
100.00 |
|
chip_sw_lc_ctrl_rma_to_scrap |
199.310s |
226.228us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_raw_to_scrap |
209.360s |
231.270us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_test_locked0_to_scrap |
177.500s |
222.355us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_rand_to_scrap |
188.160s |
196.108us |
1 |
1 |
100.00
|
| chip_lc_test_locked |
0 |
2 |
0.00 |
|
chip_rv_dm_lc_disabled |
180.040s |
243.947us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_testunlocks |
15.500s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_walkthrough |
0 |
5 |
0.00 |
|
chip_sw_lc_walkthrough_dev |
10.590s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_prod |
12.125s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_prodend |
11.052s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_rma |
9.815s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_testunlocks |
15.500s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_volatile_raw_unlock |
2 |
3 |
66.67 |
|
chip_sw_lc_ctrl_volatile_raw_unlock |
496.460s |
555.564us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz |
593.130s |
797.509us |
1 |
1 |
100.00
|
|
rom_volatile_raw_unlock |
10.160s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_rom_raw_unlock |
0 |
1 |
0.00 |
|
rom_raw_unlock |
9.533s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_exit_test_unlocked_bootstrap |
0 |
1 |
0.00 |
|
chip_sw_exit_test_unlocked_bootstrap |
62.390s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_inject_scramble_seed |
0 |
1 |
0.00 |
|
chip_sw_inject_scramble_seed |
75.394s |
0.000us |
0 |
1 |
0.00
|
| tl_d_oob_addr_access |
0 |
1 |
0.00 |
|
chip_tl_errors |
96.990s |
117.740us |
0 |
1 |
0.00
|
| tl_d_illegal_access |
0 |
1 |
0.00 |
|
chip_tl_errors |
96.990s |
117.740us |
0 |
1 |
0.00
|
| tl_d_outstanding_access |
0 |
2 |
0.00 |
|
chip_csr_aliasing |
8.140s |
0.000us |
0 |
1 |
0.00
|
|
chip_same_csr_outstanding |
10.680s |
0.000us |
0 |
1 |
0.00
|
| tl_d_partial_access |
0 |
2 |
0.00 |
|
chip_csr_aliasing |
8.140s |
0.000us |
0 |
1 |
0.00
|
|
chip_same_csr_outstanding |
10.680s |
0.000us |
0 |
1 |
0.00
|
| xbar_base_random_sequence |
1 |
1 |
100.00 |
|
xbar_random |
142.610s |
311.135us |
1 |
1 |
100.00
|
| xbar_random_delay |
6 |
6 |
100.00 |
|
xbar_smoke_zero_delays |
8.560s |
11.441us |
1 |
1 |
100.00
|
|
xbar_smoke_large_delays |
286.810s |
2241.565us |
1 |
1 |
100.00
|
|
xbar_smoke_slow_rsp |
381.220s |
2116.369us |
1 |
1 |
100.00
|
|
xbar_random_zero_delays |
30.300s |
27.409us |
1 |
1 |
100.00
|
|
xbar_random_large_delays |
1459.360s |
12158.111us |
1 |
1 |
100.00
|
|
xbar_random_slow_rsp |
1806.860s |
10611.505us |
1 |
1 |
100.00
|
| xbar_unmapped_address |
2 |
2 |
100.00 |
|
xbar_unmapped_addr |
47.740s |
31.315us |
1 |
1 |
100.00
|
|
xbar_error_and_unmapped_addr |
102.470s |
210.724us |
1 |
1 |
100.00
|
| xbar_error_cases |
2 |
2 |
100.00 |
|
xbar_error_random |
174.360s |
429.187us |
1 |
1 |
100.00
|
|
xbar_error_and_unmapped_addr |
102.470s |
210.724us |
1 |
1 |
100.00
|
| xbar_all_access_same_device |
2 |
2 |
100.00 |
|
xbar_access_same_device |
161.100s |
387.931us |
1 |
1 |
100.00
|
|
xbar_access_same_device_slow_rsp |
3159.720s |
19399.118us |
1 |
1 |
100.00
|
| xbar_all_hosts_use_same_source_id |
1 |
1 |
100.00 |
|
xbar_same_source |
24.930s |
25.793us |
1 |
1 |
100.00
|
| xbar_stress_all |
2 |
2 |
100.00 |
|
xbar_stress_all |
327.260s |
829.797us |
1 |
1 |
100.00
|
|
xbar_stress_all_with_error |
343.650s |
759.338us |
1 |
1 |
100.00
|
| xbar_stress_with_reset |
2 |
2 |
100.00 |
|
xbar_stress_all_with_rand_reset |
656.530s |
261.151us |
1 |
1 |
100.00
|
|
xbar_stress_all_with_reset_error |
982.170s |
598.009us |
1 |
1 |
100.00
|
| rom_e2e_smoke |
0 |
1 |
0.00 |
|
rom_e2e_smoke |
10.033s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_shutdown_output |
0 |
1 |
0.00 |
|
rom_e2e_shutdown_output |
10.092s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_shutdown_exception_c |
0 |
1 |
0.00 |
|
rom_e2e_shutdown_exception_c |
11.473s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_boot_policy_valid |
0 |
15 |
0.00 |
|
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 |
10.271s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_dev |
9.454s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_prod |
9.340s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_prod_end |
9.700s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_rma |
9.115s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 |
8.933s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_dev |
10.620s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_prod |
9.039s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end |
9.140s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_rma |
8.950s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 |
47.186s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_dev |
55.328s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_prod |
56.017s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end |
69.340s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_rma |
61.710s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_sigverify_always |
0 |
15 |
0.00 |
|
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 |
70.303s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_dev |
63.779s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_prod |
71.828s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_prod_end |
55.368s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_rma |
53.862s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 |
55.841s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_dev |
58.382s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_prod |
41.570s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end |
46.587s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_rma |
37.791s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 |
20.080s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_dev |
11.453s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_prod |
10.433s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end |
11.422s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_rma |
10.810s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_asm_init |
0 |
5 |
0.00 |
|
rom_e2e_asm_init_test_unlocked0 |
10.111s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_dev |
15.093s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_prod |
9.906s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_prod_end |
10.934s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_rma |
11.888s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_keymgr_init |
0 |
3 |
0.00 |
|
rom_e2e_keymgr_init_rom_ext_meas |
9.839s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_keymgr_init_rom_ext_no_meas |
9.804s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_keymgr_init_rom_ext_invalid_meas |
9.611s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_static_critical |
0 |
1 |
0.00 |
|
rom_e2e_static_critical |
9.961s |
0.000us |
0 |
1 |
0.00
|