Simulation Results: csrng

 
19/11/2025 16:06:30 sha: 241b623 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 94.45
  • block
  • 96.62
  • branch
  • 91.7
  • statement
  • 97.64
  • expression
  • 94.85
  • toggle
  • 91.77
  • fsm
  • 84.85
  • assertion
  • 91.99
  • covergroup
  • 73.62
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 30.258us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 64.210us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 40.871us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 13.000s 525.820us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 25.702us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 15.728us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 40.871us 1 1 100.00
csrng_csr_aliasing 3.000s 25.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
alerts 1 1 100.00
csrng_alert 4.000s 143.743us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 84.000s 7552.163us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 84.000s 7552.163us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 160.000s 3743.049us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 13.018us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 24.736us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 5.000s 73.830us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 5.000s 73.830us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 64.210us 1 1 100.00
csrng_csr_rw 2.000s 40.871us 1 1 100.00
csrng_csr_aliasing 3.000s 25.702us 1 1 100.00
csrng_same_csr_outstanding 6.000s 398.020us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 64.210us 1 1 100.00
csrng_csr_rw 2.000s 40.871us 1 1 100.00
csrng_csr_aliasing 3.000s 25.702us 1 1 100.00
csrng_same_csr_outstanding 6.000s 398.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 4.000s 89.695us 1 1 100.00
csrng_tl_intg_err 3.000s 154.484us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 13.960us 1 1 100.00
csrng_csr_rw 2.000s 40.871us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 4.000s 143.743us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 160.000s 3743.049us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
csrng_sec_cm 4.000s 89.695us 1 1 100.00
sec_cm_updrsp_fsm_sparse 3 3 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
csrng_sec_cm 4.000s 89.695us 1 1 100.00
sec_cm_update_fsm_sparse 3 3 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
csrng_sec_cm 4.000s 89.695us 1 1 100.00
sec_cm_blk_enc_fsm_sparse 3 3 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
csrng_sec_cm 4.000s 89.695us 1 1 100.00
sec_cm_outblk_fsm_sparse 3 3 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
csrng_sec_cm 4.000s 89.695us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
csrng_sec_cm 4.000s 89.695us 1 1 100.00
sec_cm_drbg_upd_ctr_redun 3 3 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
csrng_sec_cm 4.000s 89.695us 1 1 100.00
sec_cm_drbg_gen_ctr_redun 3 3 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
csrng_sec_cm 4.000s 89.695us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 4.000s 143.743us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 160.000s 3743.049us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 4.000s 143.743us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 154.484us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
csrng_sec_cm 4.000s 89.695us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
csrng_sec_cm 4.000s 89.695us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 58.346us 1 1 100.00
csrng_err 3.000s 45.026us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
csrng_stress_all_with_rand_reset 255.000s 16750.158us 1 1 100.00