Simulation Results: dma

 
19/11/2025 16:06:30 sha: 241b623 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 89.56
  • block
  • 97.38
  • branch
  • 95.83
  • statement
  • 96.89
  • expression
  • 91.63
  • toggle
  • 83.12
  • fsm
  • 90.14
  • assertion
  • 95.87
  • covergroup
  • 66.87
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 6.000s 588.118us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 231.727us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 329.568us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 13.317us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 15.114us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 6.000s 523.062us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 7.000s 510.702us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 191.303us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 15.114us 1 1 100.00
dma_csr_aliasing 7.000s 510.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 71.000s 21865.490us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 217.000s 19904.777us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 1011.000s 82489.749us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 1011.000s 82489.749us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 217.000s 19904.777us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 680.000s 230855.795us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 1011.000s 82489.749us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 6.000s 918.885us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 76.000s 40420.822us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 92.162us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 60.704us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 63.088us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 63.088us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 13.317us 1 1 100.00
dma_csr_rw 1.000s 15.114us 1 1 100.00
dma_csr_aliasing 7.000s 510.702us 1 1 100.00
dma_same_csr_outstanding 2.000s 45.645us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 13.317us 1 1 100.00
dma_csr_rw 1.000s 15.114us 1 1 100.00
dma_csr_aliasing 7.000s 510.702us 1 1 100.00
dma_same_csr_outstanding 2.000s 45.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 20.000s 1438.218us 1 1 100.00
dma_generic_stress 680.000s 230855.795us 1 1 100.00
dma_handshake_stress 1011.000s 82489.749us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 8.000s 402.789us 1 1 100.00
tl_intg_err 2 2 100.00
dma_sec_cm 2.000s 22.881us 1 1 100.00
dma_tl_intg_err 3.000s 165.508us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 142.000s 63978.472us 1 1 100.00
dma_longer_transfer 3.000s 70.380us 1 1 100.00
dma_stress_all_with_rand_reset 11.000s 455.394us 0 1 0.00