Simulation Results: edn

 
19/11/2025 16:06:30 sha: 241b623 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 83.51
  • line
  • 98.08
  • cond
  • 87.02
  • toggle
  • 80.54
  • fsm
  • 52.91
  • branch
  • 93.11
  • assert
  • 96.22
  • group
  • 76.72
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.990s 44.220us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.850s 16.458us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.910s 28.178us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.320s 61.257us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.080s 42.260us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.360s 23.538us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.910s 28.178us 1 1 100.00
edn_csr_aliasing 1.080s 42.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.030s 73.180us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.030s 73.180us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.030s 73.180us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.840s 30.016us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.150s 27.768us 1 1 100.00
errs 1 1 100.00
edn_err 1.040s 57.579us 1 1 100.00
disable 2 2 100.00
edn_disable 0.820s 57.803us 1 1 100.00
edn_disable_auto_req_mode 0.980s 61.783us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.190s 289.445us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.950s 36.053us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.790s 48.056us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.970s 196.074us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.970s 196.074us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.850s 16.458us 1 1 100.00
edn_csr_rw 0.910s 28.178us 1 1 100.00
edn_csr_aliasing 1.080s 42.260us 1 1 100.00
edn_same_csr_outstanding 1.260s 25.646us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.850s 16.458us 1 1 100.00
edn_csr_rw 0.910s 28.178us 1 1 100.00
edn_csr_aliasing 1.080s 42.260us 1 1 100.00
edn_same_csr_outstanding 1.260s 25.646us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 2.550s 137.942us 1 1 100.00
edn_sec_cm 6.520s 1053.785us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 47.350us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.150s 27.768us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.520s 1053.785us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.520s 1053.785us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.520s 1053.785us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.520s 1053.785us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.150s 27.768us 1 1 100.00
edn_sec_cm 6.520s 1053.785us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.150s 27.768us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.550s 137.942us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 18.440s 1146.531us 1 1 100.00