Simulation Results: hmac

 
19/11/2025 16:06:30 sha: 241b623 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 89.99
  • line
  • 99.68
  • cond
  • 96.29
  • toggle
  • 100.0
  • fsm
  • 94.12
  • branch
  • 99.34
  • assert
  • 96.42
  • group
  • 44.07
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.710s 1714.657us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.890s 21.930us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.840s 79.658us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.910s 1098.728us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.300s 296.728us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.350s 87.277us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.840s 79.658us 1 1 100.00
hmac_csr_aliasing 5.300s 296.728us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 36.680s 1796.296us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 45.800s 4283.870us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 178.520s 17324.553us 1 1 100.00
hmac_test_sha384_vectors 392.290s 104218.254us 1 1 100.00
hmac_test_sha512_vectors 364.020s 10353.781us 1 1 100.00
hmac_test_hmac256_vectors 10.110s 1229.480us 1 1 100.00
hmac_test_hmac384_vectors 7.710s 242.004us 1 1 100.00
hmac_test_hmac512_vectors 9.010s 246.364us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 18.000s 432.294us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 822.010s 5876.280us 1 1 100.00
error 1 1 100.00
hmac_error 38.470s 2945.390us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 100.830s 34430.164us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.710s 1714.657us 1 1 100.00
hmac_long_msg 36.680s 1796.296us 1 1 100.00
hmac_back_pressure 45.800s 4283.870us 1 1 100.00
hmac_datapath_stress 822.010s 5876.280us 1 1 100.00
hmac_burst_wr 18.000s 432.294us 1 1 100.00
hmac_stress_all 946.330s 30703.064us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.710s 1714.657us 1 1 100.00
hmac_long_msg 36.680s 1796.296us 1 1 100.00
hmac_back_pressure 45.800s 4283.870us 1 1 100.00
hmac_datapath_stress 822.010s 5876.280us 1 1 100.00
hmac_wipe_secret 100.830s 34430.164us 1 1 100.00
hmac_test_sha256_vectors 178.520s 17324.553us 1 1 100.00
hmac_test_sha384_vectors 392.290s 104218.254us 1 1 100.00
hmac_test_sha512_vectors 364.020s 10353.781us 1 1 100.00
hmac_test_hmac256_vectors 10.110s 1229.480us 1 1 100.00
hmac_test_hmac384_vectors 7.710s 242.004us 1 1 100.00
hmac_test_hmac512_vectors 9.010s 246.364us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.710s 1714.657us 1 1 100.00
hmac_long_msg 36.680s 1796.296us 1 1 100.00
hmac_back_pressure 45.800s 4283.870us 1 1 100.00
hmac_datapath_stress 822.010s 5876.280us 1 1 100.00
hmac_burst_wr 18.000s 432.294us 1 1 100.00
hmac_error 38.470s 2945.390us 1 1 100.00
hmac_wipe_secret 100.830s 34430.164us 1 1 100.00
hmac_test_sha256_vectors 178.520s 17324.553us 1 1 100.00
hmac_test_sha384_vectors 392.290s 104218.254us 1 1 100.00
hmac_test_sha512_vectors 364.020s 10353.781us 1 1 100.00
hmac_test_hmac256_vectors 10.110s 1229.480us 1 1 100.00
hmac_test_hmac384_vectors 7.710s 242.004us 1 1 100.00
hmac_test_hmac512_vectors 9.010s 246.364us 1 1 100.00
hmac_stress_all 946.330s 30703.064us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 946.330s 30703.064us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.680s 22.647us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.880s 41.606us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.270s 889.761us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.270s 889.761us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.890s 21.930us 1 1 100.00
hmac_csr_rw 0.840s 79.658us 1 1 100.00
hmac_csr_aliasing 5.300s 296.728us 1 1 100.00
hmac_same_csr_outstanding 0.990s 74.529us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.890s 21.930us 1 1 100.00
hmac_csr_rw 0.840s 79.658us 1 1 100.00
hmac_csr_aliasing 5.300s 296.728us 1 1 100.00
hmac_same_csr_outstanding 0.990s 74.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.870s 150.864us 1 1 100.00
hmac_tl_intg_err 3.120s 670.464us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.120s 670.464us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.710s 1714.657us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.440s 230.035us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 77.960s 18117.396us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.840s 523.284us 1 1 100.00