| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| keymgr_dpe_smoke | 30.610s | 8998.257us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 0.790s | 54.574us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_rw | 0.780s | 11.293us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_bit_bash | 6.070s | 294.891us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_aliasing | 3.850s | 158.897us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_mem_rw_with_rand_reset | 1.250s | 74.115us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| keymgr_dpe_csr_rw | 0.780s | 11.293us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 3.850s | 158.897us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| intr_test | 1 | 1 | 100.00 | |||
| keymgr_dpe_intr_test | 0.850s | 110.394us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| keymgr_dpe_alert_test | 0.930s | 23.409us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| keymgr_dpe_tl_errors | 3.220s | 460.776us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| keymgr_dpe_tl_errors | 3.220s | 460.776us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 0.790s | 54.574us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_rw | 0.780s | 11.293us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 3.850s | 158.897us | 1 | 1 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 1.650s | 69.477us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 0.790s | 54.574us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_rw | 0.780s | 11.293us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 3.850s | 158.897us | 1 | 1 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 1.650s | 69.477us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| keymgr_dpe_sec_cm | 4.880s | 301.145us | 1 | 1 | 100.00 | |
| keymgr_dpe_tl_intg_err | 4.200s | 962.561us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 1.250s | 40.236us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 1.250s | 40.236us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 1.250s | 40.236us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 1.250s | 40.236us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors_with_csr_rw | 3.440s | 367.630us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| keymgr_dpe_sec_cm | 4.880s | 301.145us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| keymgr_dpe_sec_cm | 4.880s | 301.145us | 1 | 1 | 100.00 | |